Renesas H8S Series Hardware Manual page 666

Section 18 LPC Interface (LPC)
• Host base address registers 1H and 1L (HBAR1H, HBAR1L)
• Host base address registers 2H and 2L (HBAR2H, HBAR2L)
• On-chip RAM host base address registers H and L (RAMBARH, RAMBARL)
• Address space set register (ASSR)
• On-chip RAM address space set register (RAMASSR)
• Slave address register 1 (SAR1)
• Slave address register 2 (SAR2)
• On-chip RAM slave address register (RAMAR)
• Flash memory write protect registers H, M, and L (FWPRH, FWPRM, FWPRL)
• Flash memory read protect registers H, M, and L (FRPRH, FRPRM, FRPRL)
• On-chip RAM protect control register (MPCR)
• User command data register (UCMDTR)
Notes: R/W in the register description means as follows:
1. R/W slave indicates access from the slave (this LSI).
2. R/W host indicates access from the host.
Rev. 3.00 Jul. 14, 2005 Page 618 of 986
REJ09B0098-0300