Renesas H8S Series Hardware Manual page 24
16-bit single-chip microcomputer
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Also See for H8S Series:
- Hardware manual (1047 pages) ,
- User manual (38 pages) ,
- User manual (26 pages)
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17.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 587
17.3.3 Keyboard Control Register H (KBCRH) .............................................................. 588
17.3.4 Keyboard Control Register L (KBCRL)............................................................... 590
17.3.5 Keyboard Data Buffer Register (KBBR) .............................................................. 592
17.3.6 Keyboard Buffer Transmit Data Register (KBTR)............................................... 592
17.4 Operation ........................................................................................................................... 593
17.4.1 Receive Operation ................................................................................................ 593
17.4.2 Transmit Operation............................................................................................... 595
17.4.3 Receive Abort ....................................................................................................... 597
17.4.4 KCLKI and KDI Read Timing ............................................................................. 600
17.4.5 KCLKO and KDO Write Timing ......................................................................... 601
17.4.6 KBF Setting Timing and KCLK Control.............................................................. 602
17.4.7 Receive Timing..................................................................................................... 603
17.4.8 Operation during Data Reception ......................................................................... 604
17.4.9 KCLK Fall Interrupt Operation ............................................................................ 605
17.4.10 First KCLK Falling Interrupt................................................................................ 606
17.5 Usage Notes ....................................................................................................................... 611
17.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................. 611
17.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 612
17.5.3 Module Stop Mode Setting ................................................................................... 612
17.5.4 Medium Speed Mode............................................................................................ 612
17.5.5 Transmit Completion Flag (KBTE) ...................................................................... 612
Section 18 LPC Interface (LPC)........................................................................ 613
18.1 Features.............................................................................................................................. 613
18.2 Input/Output Pins............................................................................................................... 616
18.3 Register Descriptions......................................................................................................... 617
18.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 619
18.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 625
18.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 628
18.3.4 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 629
18.3.5 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 631
18.3.6 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 632
18.3.7 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 633
18.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 633
18.3.9 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 634
18.3.10 SERIRQ Control Register 0 (SIRQCR0).............................................................. 640
18.3.11 SERIRQ Control Register 1 (SIRQCR1).............................................................. 644
18.3.12 SERIRQ Control Register 2 (SIRQCR2).............................................................. 649
18.3.13 Host Interface Select Register (HISEL)................................................................ 653
Rev. 3.00 Jul. 14, 2005 Page xxiv of xlviii
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