Table 16.5 Flags And Transfer States (Slave Mode) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)

Table 16.5 Flags and Transfer States (Slave Mode)

MST TRS BBSY ESTP
0 0 0 0
0 0 1↑ 0
0 1↑/0 1 0
1
*
0 0 1 0
0 1↑/0 1 0
1
*
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 0 1 0
0 0 1 0
Rev. 3.00 Jul. 14, 2005 Page 524 of 986
REJ09B0098-0300
STOP IRTR AASX AL
0 0 0 0
0 0 0↓ 0
0 0 0 —
0 0 0 —
0 1↑ 1↑ —
0 — — —
0 1↑/0 — —
2
*
0 — — 0↓
0 — — —
0 — — 0↓
0 1↑/0 — 0
2
*
0 1↑/0 — —
2
*
0 — — 0↓
AAS ADZ ACKB ICDRF ICDRE State
0 0 0 —
0 0 0 —
1↑ 0 0 1↑
1↑ 1↑ 0 1↑
0 0 0 1↑
— 0 1↑ —
— 0 0 —
0↓ 0 0 —
— 1 0
0↓ 0 0
0 0 0
— — — 1↑
0↓ 0↓ — 0↓
0 Idle state (flag
clearing
required)
1↑ Start condition
detected
1 SAR match in
first frame
(SARX≠SAR)
1 General call
address match
in first frame
(SARX≠H'00)
1 SAR match in
first frame
(SAR≠SARX)
— Transmission
end (ACKE=1
and ACKB=1)
1↑ Transmission
end with
ICDRE=0
0↓ ICDR write with
the above state
1 Transmission
end with
ICDRE=1
0↓ ICDR write with
the above state
1↑ Automatic data
transfer from
ICDRT to ICDRS
with the above
state
— Reception end
with ICDRF=0
— ICDR read with
the above state