Timer Input Select Register (Tisr); Timer Connection Register I (Tconri) - Renesas H8S Series Hardware Manual

13.3.8

Timer Input Select Register (TISR)

TISR permits or prohibits a signal source of external clock/reset input for the counter.
Bit Bit Name Initial Value R/W
7 to 1 — All 1
0 IS 0
13.3.9

Timer Connection Register I (TCONRI)

TCONRI controls the input capture function.
Bit Bit Name
7 to 5 —
4 ICST
3 to 0 —
Description
R/(W) Reserved
The initial value should not be changed.
R/W Input Select
Selects a timer clock/reset input pin (TMIY) as the signal
source of external clock/reset input for the TMR_Y
counter.
0: Input is prohibited
1: TMIY (TMCIY/TMRIY) is permitted for input
Initial Value R/W
All 0 R/W
0 R/W
All 0 R/W
Description
Reserved
The initial value should not be changed.
Input Capture Start Bit
TMR_X has input capture registers (TICRR and
TICRF). TICRR and TICRF can measure the width of
a pulse by means of a single capture operation under
the control of the ICST bit. When a rising edge
followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those
points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Reserved
The initial values should not be modified.
Rev. 3.00 Jul. 14, 2005 Page 395 of 986
Section 13 8-Bit Timer (TMR)
REJ09B0098-0300