Pwmx (D/A) Counter (Dacnt) - Renesas H8S Series Hardware Manual

10.3.1

PWMX (D/A) Counter (DACNT)

DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select
bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a
channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-
bit precision, it uses the lower 12 bits and ignores the upper 2-bit counter. As DACNT is 16 bits,
data transfer between the CPU is performed through the temporary register (TEMP). For details,
see section 10.4, Bus Master Interface.
Bit (CPU): 15 14
Bit (counter): 7 6
• DACNTH
Bit Bit Name
7 to 0 DACNT7 to
DACNT0
• DACNTL
Bit Bit Name
7 to 2 DACNT 8 to
DACNT 13

1
0 REGS
DACNTH
13 12 11 10
5 4 3 2
Initial Value R/W
All 0 R/W
Initial Value R/W
All 0 R/W
1 R
1 R/W
Section 10 14-Bit PWM Timer (PWMX)
9 8 7 6
1 0 8 9
Description
Upper Up-Counter
Description
Lower Up-Counter
Reserved
Always read as 1 and cannot be modified.
Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit
specifies which registers can be accessed.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 3.00 Jul. 14, 2005 Page 261 of 986
DACNTL
5 4 3 2
10 11 12 13
REJ09B0098-0300
1 0
REGS