Timing Of Input Capture Flag (Icf) Setting; Figure 11.10 Buffered Input Capture Timing (Bufea = 1); Figure 11.11 Timing Of Input Capture Flag (Icfa, Icfb, Icfc, Or Icfd) Setting - Renesas H8S Series Hardware Manual

Section 11 16-Bit Free-Running Timer (FRT)
φ
FTIA
Input capture
signal

Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)

11.5.6

Timing of Input Capture Flag (ICF) Setting

The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is
simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure
11.11 shows the timing of setting the ICFA to ICFD flag.
φ
Input capture
signal
ICFA to ICFD
FRC
ICRA to ICRD

Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting

Rev. 3.00 Jul. 14, 2005 Page 294 of 986
REJ09B0098-0300
CPU read cycle of ICRA or ICRC
T 1 T 2
N
N