Conflict Between Frc Write And Increment; Figure 11.18 Conflict Between Frc Write And Increment - Renesas H8S Series Hardware Manual

Section 11 16-Bit Free-Running Timer (FRT)
11.7.2

Conflict between FRC Write and Increment

If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.

Figure 11.18 Conflict between FRC Write and Increment

Rev. 3.00 Jul. 14, 2005 Page 300 of 986
REJ09B0098-0300
Write cycle of FRC
T 1
φ
Address FRC address
Internal write
signal
FRC input
clock
FRC
T 2
N M
Write data