Table 15.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Bit
4
Rate
(bit/s) n
N
110
250
2
29
500
2
124
1k
1
249
2.5k
1
99
5k
0
199
10k
0
99
25k
0
39
50k
0
19
100k
0
9
250k
0
3
500k
0
1∗
1M
0
0
2.5M
5M
[Legend]
Blank: Setting prohibited.
 :
Can be set, but there will be a degree of error.
*:
Continuous transfer or reception is not possible.
Operating Frequency φ (MHz)
8
n
N
n
3
124
2
249
2
124
1
199
1
1
99
1
0
199
0
0
79
0
0
39
0
0
19
0
0
7
0
0
3
0
0
1
0
Section 15 Serial Communication Interface (SCI, IrDA)
10
N
n
3
3
2
249
2
124
1
249
1
99
0
49
0
24
0
9
0
4
0
0
0*
Rev. 3.00 Jul. 14, 2005 Page 451 of 986
16
20
N
n
N
249
124
249
99
2
124
199
1
249
99
1
124
159
0
199
79
0
99
39
0
49
15
0
19
7
0
9
3
0
4
0
1
0
0*
REJ09B0098-0300

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