Iric Setting Timing And Scl Control; Figure 16.25 Iric Setting Timing And Scl Control (1) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
16.4.7

IRIC Setting Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 16.25 to 16.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
7
SDA
7
IRIC
User processing
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
7
SDA
7
IRIC
User processing
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.

Figure 16.25 IRIC Setting Timing and SCL Control (1)

Rev. 3.00 Jul. 14, 2005 Page 562 of 986
REJ09B0098-0300
2
C bus format, no wait)
8 9
8 A
Clear IRIC
8 9
8 A
Clear IRIC
1 2
1 2
Write to ICDR (transmit)
or read from ICDR (receive)
3
3
1
1
Clear IRIC