Renesas H8S Series Hardware Manual page 695

Bit Bit Name Initial Value Slave Host Description
2 IRQ10E2 0
1 IRQ9E2 0
R/W

R/W Host IRQ10 Interrupt Enable 2
Enables or disables an HIRQ10 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ10 interrupt request by OBF2 and
IRQE10E2 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ10 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ10 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ10E2 = 0

R/W Host IRQ9 Interrupt Enable 2
Enables or disables an HIRQ9 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ9 interrupt request by OBF2 and IRQE9E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ9E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ9 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ9 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ9E2 = 0
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 647 of 986
REJ09B0098-0300