Transmit Operation; Figure 17.4 Receive Timing - Renesas H8S Series Hardware Manual

KCLK
1
(pin state)
Start
KD
bit
(pin state)
KCLK
(input)
KCLK
(output)
Previous data
KB7 to KB0
PER
KBS
KBF
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17.4.2

Transmit Operation

In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6.
2 3
0 1
KB0 KB1

Figure 17.4 Receive Timing

Section 17 Keyboard Buffer Control Unit (KBU)
Receive processing/
error handling
9 10 11
7
Parity bit Stop bit
Automatic I/O inhibit
Receive data
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Rev. 3.00 Jul. 14, 2005 Page 595 of 986
Flag cleared
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REJ09B0098-0300