Figure 21.16 Transitions To Error-Protection State - Renesas H8S Series Hardware Manual

Section 21 Flash Memory (0.18-µm F-ZTAT Version)
• When a bus master other than the CPU, such as the DTC or LPC, gets the bus during
programming/erasing
Error protection is cancelled only by a reset or a transition to hardware-standby mode.
Note that the reset should be released after a reset period of 100 µs which is longer than normal.
Since high voltages are applied during programming/erasing of the flash memory, some voltage
may remain after the error-protection state has been entered. For this reason, it is necessary to
reduce the risk of damage to the flash memory by extending the reset period so that the charge is
released.
The state transition diagram in figure 21.16 shows transitions to and from the error-protection
state.
Program mode
Erase mode
Read disabled
Programming/erasing enabled
FLER = 0
Error occurred
Error-protection state
Read enabled
Programming/erasing disabled
FLER = 1
Rev. 3.00 Jul. 14, 2005 Page 794 of 986
REJ09B0098-0300
RES = 0 or STBY = 0
Software standby mode
Software-standby mode
canceled

Figure 21.16 Transitions to Error-Protection State

Reset or hardware
standby mode
(Hardware protection)
Read disabled
Programming/erasing disabled
FLER = 0
RES = 0 or
Programming/erasing interface
STBY = 0
registers are in the initial state.
Error-protection state
(Software standby)
Read disabled
Programming/erasing disabled
FLER = 1
Programming/erasing interface
registers are in the initial state.