Renesas H8S Series Hardware Manual page 678

Section 18 LPC Interface (LPC)
Bit Bit Name Initial Value Slave Host Description
0 TWRE 0
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
in LADR3 is inverted, and the values of bits 3 to 0 are ignored.
• Host select register
I/O Address
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 0
Bit 4 Bit 3 1
Bit 4 Bit 3 0
Bit 4 Bit 3 1
Bit 4
0 0
Bit 4
0 0
: :
1 1
Bit 4
0 0
Bit 4
0 0
: :
1 1
Note: When channel 3 is used, the content of LADR3 must be set so that the addresses for
*
channels 1, 2, and 4 are different.
Rev. 3.00 Jul. 14, 2005 Page 630 of 986
REJ09B0098-0300
R/W

R/W Bidirectional Data Register Enable
Enables or disables bidirectional data register
operation.
0: TWR operation is disabled
TWR-related I/O address match determination is
halted
1: TWR operation is enabled
Transfer
Bit 1 Bit 0 Cycle
Bit 1 0 I/O write
Bit 1 0 I/O write
Bit 1 0 I/O read
Bit 1 0 I/O read
0 0 I/O write
0 1 I/O write
: :
1 1
0 0 I/O read
0 1 I/O read
: :
1 1
Host Select Register
IDR3 write, C/D3 ← 0
IDR3 write, C/D3 ← 1
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15 write
TWR0SW read
TWR1 to TWR15 read