Figure 12.19 Example Of Buffer Operation (1) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Examples of Buffer Operation

1. When TGR is an output compare register

Figure 12.19 shows an operation example in which PWM mode 1 has been designated for

channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used

in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0

output at compare match B. As buffer operation has been set, when compare match A occurs

the output changes and the value in buffer register TGRC is simultaneously transferred to

timer general register TGRA. This operation is repeated each time compare match A occurs.

For details of PWM modes, see section 12.5.4, PWM Modes.

Figure 12.19 Example of Buffer Operation (1)

Section 12 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jul. 14, 2005 Page 345 of 986

REJ09B0098-0300

H8s/2100 series H8s/2114r R4f2114r