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Manuals and User Guides for Renesas H8S/2114R. We have
1
Renesas H8S/2114R manual available for free PDF download: Hardware Manual
Renesas H8S/2114R Hardware Manual (1038 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.77 MB
Table of Contents
General Precautions on Handling of Product
4
Preface
6
Table of Contents
11
Section 1 Overview
49
Overview
49
Section 1 Overview
50
Internal Block Diagram
51
Figure 1.1 H8S/2114R Group Internal Block Diagram
51
Pin Description
52
Pin Arrangement
52
Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)
52
Pin Arrangement in each Operating Mode
53
Table 1.1 H8S/2114R Group Pin Arrangement in each Operating Mode
53
Overview
53
Pin Functions
58
Table 1.2 Pin Functions
58
Electrical Characteristics
59
Figure 1.3 Sample Design of Reset Signals with no Affection each Other
65
Section 2 CPU
67
Features
67
Differences between H8S/2600 CPU and H8S/2000 CPU
68
Differences from H8/300 CPU
69
Differences from H8/300H CPU
69
CPU Operating Modes
70
Normal Mode
70
Figure 2.1 Exception Vector Table (Normal Mode)
71
Figure 2.2 Stack Structure in Normal Mode
71
Advanced Mode
72
Figure 2.3 Exception Vector Table (Advanced Mode)
72
Figure 2.4 Stack Structure in Advanced Mode
73
Address Space
74
Figure 2.5 Memory Map
74
Register Configuration
75
Figure 2.6 CPU Internal Registers
75
Figure 2.7 Usage of General Registers
76
General Registers
76
Extended Control Register (EXR)
77
Figure 2.8 Stack
77
Program Counter (PC)
77
Condition-Code Register (CCR)
78
Initial Register Values
79
Data Formats
80
General Register Data Formats
80
Figure 2.9 General Register Data Formats (1)
80
Figure 2.9 General Register Data Formats (2)
81
Memory Data Formats
82
Figure 2.10 Memory Data Formats
82
Instruction Set
83
Table 2.1 Instruction Classification
83
Table 2.2 Operation Notation
84
Table of Instructions Classified by Function
84
Table 2.3 Data Transfer Instructions
85
Table 2.4 Arithmetic Operations Instructions (1)
86
Table 2.4 Arithmetic Operations Instructions (2)
87
Table 2.5 Logic Operations Instructions
88
Table 2.6 Shift Instructions
89
Table 2.7 Bit Manipulation Instructions (1)
90
Table 2.7 Bit Manipulation Instructions (2)
91
Table 2.8 Branch Instructions
92
Table 2.9 System Control Instructions
93
Table 2.10 Block Data Transfer Instructions
94
Basic Instruction Formats
95
Figure 2.11 Instruction Formats (Examples)
95
Addressing Modes and Effective Address Calculation
96
Register Direct-Rn
96
Register Indirect-@Ern
96
Table 2.11 Addressing Modes
96
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
97
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
97
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
97
Immediate-#XX:8, #XX:16, or #XX:32
98
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
98
Table 2.12 Absolute Address Access Ranges
98
Memory Indirect-@@Aa:8
99
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
99
Effective Address Calculation
100
Table 2.13 Effective Address Calculation (1)
100
Table 2.13 Effective Address Calculation (2)
101
Processing States
102
Figure 2.13 State Transitions
103
Usage Notes
104
Note on TAS Instruction Usage
104
Note on STM/LDM Instruction Usage
104
Note on Bit Manipulation Instructions
104
EEPMOV Instruction
105
Section 3 MCU Operating Modes
107
Operating Mode Selection
107
Register Descriptions
108
Mode Control Register (MDCR)
108
System Control Register (SYSCR)
109
Serial Timer Control Register (STCR)
111
System Control Register 3 (SYSCR3)
114
Operating Mode Descriptions
115
Mode 2
115
Mode 3
115
Address Map
115
Figure 3.1 Address Map
116
Section 4 Exception Handling
117
Exception Handling Types and Priority
117
Table 4.1 Exception Types and Priority
117
Exception Sources and Exception Vector Table
118
Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode)
118
Table 4.3 Exception Handling Vector Table (Extended Vector Mode)
120
Reset
122
Reset Exception Handling
122
Interrupts Immediately after Reset
123
On-Chip Peripheral Modules after Reset Is Cancelled
123
Figure 4.1 Reset Sequence (Mode 2)
123
Interrupt Exception Handling
124
Trap Instruction Exception Handling
124
Table 4.4 Status of CCR after Trap Instruction Exception Handling
124
Stack Status after Exception Handling
125
Figure 4.2 Stack Status after Exception Handling
125
Usage Note
126
Figure 4.3 Operation When SP Value Is Odd
126
Section 5 Interrupt Controller
127
Features
127
Figure 5.1 Block Diagram of Interrupt Controller
128
Input/Output Pins
129
Table 5.1 Pin Configuration
129
Register Descriptions
130
Interrupt Control Registers a to D (ICRA to ICRD)
131
Table 5.2 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0)
131
Table 5.3 Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1)
132
Address Break Control Register (ABRKCR)
133
Break Address Registers a to C (BARA to BARC)
134
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
135
IRQ Enable Registers (IER16, IER)
138
IRQ Status Registers (ISR16, ISR)
139
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB)
141
Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts
143
Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (Extended Vector Mode: EIVS = 1)
144
IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
145
Interrupt Sources
147
External Interrupt Sources
147
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0
148
Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8)
149
Internal Interrupt Sources
150
Interrupt Exception Handling Vector Tables
150
Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode)
151
Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode)
154
Interrupt Control Modes and Interrupt Operation
157
Table 5.6 Interrupt Control Modes
157
Figure 5.6 Block Diagram of Interrupt Control Operation
158
Table 5.7 Interrupts Selected in each Interrupt Control Mode
159
Interrupt Control Mode 0
160
Table 5.8 Operations and Control Signal Functions in each Interrupt Control Mode
160
Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
161
Figure 5.8 State Transition in Interrupt Control Mode 1
162
Interrupt Control Mode 1
162
Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1
164
Interrupt Exception Handling Sequence
165
Figure 5.10 Interrupt Exception Handling
166
Interrupt Response Times
167
Table 5.9 Interrupt Response Times
167
DTC Activation by Interrupt
168
Figure 5.11 Interrupt Control for DTC
168
Table 5.10 Interrupt Source Selection and Clearing Control
169
Address Breaks
170
Features
170
Block Diagram
170
Figure 5.12 Block Diagram of Address Break Function
170
Operation
171
Usage Notes
171
Figure 5.13 Examples of Address Break Timing
172
Usage Notes
173
Conflict between Interrupt Generation and Disabling
173
Figure 5.14 Conflict between Interrupt Generation and Disabling
173
Instructions for Disabling Interrupts
174
Interrupts During Execution of EEPMOV Instruction
174
Vector Address Switching
174
External Interrupt Pin in Software Standby Mode and Watch Mode
175
Noise Canceller Switching
175
IRQ Status Register (ISR)
175
Section 6 Bus Controller (BSC)
177
Features
177
Figure 6.1 Block Diagram of BSC
177
Register Descriptions
178
Bus Control Register (BCR)
178
Wait State Control Register (WSCR)
179
Bus Arbitration
180
Priority of Bus Masters
180
Bus Transfer Timing
180
Section 7 Data Transfer Controller (DTC)
183
Features
184
Figure 7.1 Block Diagram of DTC
184
Register Descriptions
185
DTC Mode Register a (MRA)
186
DTC Mode Register B (MRB)
187
DTC Source Address Register (SAR)
187
DTC Destination Address Register (DAR)
188
DTC Transfer Count Register a (CRA)
188
DTC Transfer Count Register B (CRB)
188
DTC Enable Registers (DTCER)
189
Table 7.1 Correspondence between Interrupt Sources and DTCER
189
DTC Vector Register (DTVECR)
190
Activation Sources
191
Figure 7.2 Block Diagram of DTC Activation Source Control
191
Location of Register Information and DTC Vector Table
192
Figure 7.3 DTC Register Information Location in Address Space
192
Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
193
Operation
195
Figure 7.4 DTC Operation Flowchart
195
Figure 7.5 Memory Mapping in Normal Mode
196
Normal Mode
196
Table 7.3 Register Functions in Normal Mode
196
Figure 7.6 Memory Mapping in Repeat Mode
197
Repeat Mode
197
Table 7.4 Register Functions in Repeat Mode
197
Block Transfer Mode
198
Figure 7.7 Memory Mapping in Block Transfer Mode
198
Table 7.5 Register Functions in Block Transfer Mode
198
Chain Transfer
199
Figure 7.8 Chain Transfer Operation
199
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
200
Interrupt Sources
200
Operation Timing
200
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
201
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
201
Number of DTC Execution States
202
Table 7.6 DTC Execution Status
202
Table 7.7 Number of States Required for each Execution Status
202
Procedures for Using DTC
203
Activation by Interrupt
203
Activation by Software
203
Examples of Use of the DTC
204
Normal Mode
204
Software Activation
205
Usage Notes
206
Module Stop Mode Setting
206
On-Chip RAM
206
DTCE Bit Setting
206
Setting Required on Entering Subactive Mode or Watch Mode
206
DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter
206
Section 8 I/O Ports
207
Table 8.1 Port Functions
207
Port 1
212
Port 1 Data Direction Register (P1DDR)
212
Port 1 Data Register (P1DR)
213
Port 1 Pull-Up MOS Control Register (P1PCR)
213
Pin Functions
214
Port 1 Input Pull-Up MOS
214
Table 8.2 Port 1 Input Pull-Up MOS States
214
Port 2
215
Port 2 Data Direction Register (P2DDR)
215
Port 2 Data Register (P2DR)
216
Port 2 Pull-Up MOS Control Register (P2PCR)
216
Pin Functions
217
Port 2 Input Pull-Up MOS
218
Table 8.3 Port 2 Input Pull-Up MOS States
218
Port 3
219
Port 3 Data Direction Register (P3DDR)
219
Port 3 Data Register (P3DR)
220
Port 3 Pull-Up MOS Control Register (P3PCR)
220
Pin Functions
221
Port 3 Input Pull-Up MOS
221
Table 8.4 Port 3 Input Pull-Up MOS States
221
Port 4
222
Port 4 Data Direction Register (P4DDR)
222
Port 4 Data Register (P4DR)
223
Pin Functions
223
Port 5
226
Port 5 Data Direction Register (P5DDR)
226
Port 5 Data Register (P5DR)
226
Pin Functions
227
Port 6
228
Port 6 Data Direction Register (P6DDR)
228
Port 6 Data Register (P6DR)
229
Pull-Up MOS Control Register (KMPCR)
229
Noise Canceller Enable Register (P6NCE)
230
Noise Canceller Mode Control Register (P6NCMC)
230
Noise Cancel Cycle Setting Register (P6NCCS)
231
Figure 8.1 Noise Cancel Circuit
232
Figure 8.2 Noise Cancel Operation
232
System Control Register 2 (SYSCR2)
233
Pin Functions
233
Port 6 Input Pull-Up MOS
236
Table 8.5 Port 6 Input Pull-Up MOS States
236
Port 7
237
Port 7 Input Data Register (P7PIN)
237
Pin Functions
238
Port 8
239
Port 8 Data Direction Register (P8DDR)
239
Port 8 Data Register (P8DR)
240
Pin Functions
241
Port 9
244
Port 9 Data Direction Register (P9DDR)
244
Port 9 Data Register (P9DR)
245
Port 9 Pull-Up MOS Control Register (P9PCR)
245
Pin Functions
246
Port 9 Input Pull-Up MOS
248
Table 8.6 Port 9 Input Pull-Up MOS States
248
Port a
249
Port a Data Direction Register (PADDR)
249
Port a Output Data Register (PAODR)
250
Port a Input Data Register (PAPIN)
250
Pin Functions
251
Port B
252
Port B Data Direction Register (PBDDR)
252
Port B Output Data Register (PBODR)
253
Port B Input Data Register (PBPIN)
253
Pin Functions
254
Port B Input Pull-Up MOS
256
Table 8.7 Port B Input Pull-Up MOS States
256
Port C
257
Port C Data Direction Register (PCDDR)
257
Port C Output Data Register (PCODR)
258
Port C Input Data Register (PCPIN)
258
Noise Canceller Enable Register (PCNCE)
259
Noise Canceller Mode Control Register (PCNCMC)
259
Noise Cancel Cycle Setting Register (PCNCCS)
260
Pin Functions
260
Port C Nch-OD Control Register (PCNOCR)
263
Pin Functions
263
8.12.10 Port C Input Pull-Up MOS
264
Table 8.8 Port C Input Pull-Up MOS States
264
Port D
265
Port D Data Direction Register (PDDDR)
265
Port D Output Data Register (PDODR)
266
Port D Input Data Register (PDPIN)
266
Pin Functions
267
Port D Nch-OD Control Register (PDNOCR)
271
Pin Functions
271
Port D Input Pull-Up MOS
272
Table 8.9 Port D Input Pull-Up MOS States
272
Port E
273
Port E Input Pull-Up MOS Control Register (PEPCR)
273
Port E Input Data Register (PEPIN)
273
Pin Functions
274
Port E Input Pull-Up MOS
274
Table 8.10 Port E Input Pull-Up MOS States
274
Port F
275
Port F Data Direction Register (PFDDR)
275
Port F Output Data Register (PFODR)
276
Port F Input Data Register (PFPIN)
276
Pin Functions
277
Port F Nch-OD Control Register (PFNOCR)
279
Pin Functions
279
Port F Input Pull-Up MOS
280
Table 8.11 Port F Input Pull-Up MOS States
280
Port G
281
Port G Data Direction Register
281
Port G Output Data Register
282
Port G Input Data Register
282
Noise Canceller Enable Register
283
Noise Canceller Mode Control Register
283
Noise Cancel Cycle Setting Register
284
Pin Functions
285
Port G Nch-OD Control Register
290
Pin Functions
290
Change of Peripheral Function Pins
291
Port Control Register 0 (PTCNT0)
291
Port Control Register 1 (PTCNT1)
292
Port Control Register 2 (PTCNT2)
293
Section 9 8-Bit PWM Timer (PWM)
295
Features
295
Figure 9.1 Block Diagram of PWM Timer
296
Input/Output Pins
297
Register Descriptions
297
Table 9.1 Pin Configuration
297
PWM Register Select (PWSL)
298
PWM Data Registers 15 to 8 (PWDR15 to PWDR8)
299
Table 9.2 Internal Clock Selection
299
Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency When Φ = 20 Mhz
299
PWM Data Polarity Register B (PWDPRB)
300
PWM Output Enable Register B (PWOERB)
300
Peripheral Clock Select Register (PCSR)
301
Operation
302
Table 9.4 Duty Cycle of Basic Pulse
302
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000)
303
Table 9.5 Position of Pulses Added to Basic Pulses
303
Diagram of PWM Used as D/A Converter
304
Figure 9.3 Example of PWM Setting
304
Figure 9.4 Example When PWM Is Used as D/A Converter
304
PWM Setting Example
304
Usage Notes
305
Module Stop Mode Setting
305
Section 10 14-Bit PWM Timer (PWMX)
307
Features
307
Figure 10.1 PWMX (D/A) Block Diagram
307
Input/Output Pins
308
Register Descriptions
308
Table 10.1 Pin Configuration
308
PWMX (D/A) Counter (DACNT)
309
PWMX (D/A) Data Registers a and B (DADRA and DADRB)
310
PWMX (D/A) Control Register (DACR)
312
Peripheral Clock Select Register (PCSR)
313
Table 10.2 Clock Select of PWMX
313
Bus Master Interface
314
Figure 10.2 (1) DACNT Access Operation (1) [CPU → DACNT(H'AA57) Writing]
315
Table 10.3 Reading/Writing to 16-Bit Registers
315
Figure 10.2 (2) DACNT Access Operation (2) [DACNT → CPU(H'AA57) Reading]
316
Operation
317
Figure 10.3 PWMX (D/A) Operation
317
Table 10.4 Settings and Operation (Examples When Φ = 20 Mhz)
318
Figure 10.4 Output Waveform (os = 0, DADR Corresponds to T L )
320
Figure 10.5 Output Waveform (os = 1, DADR Corresponds to T H )
321
Figure 10.6 D/A Data Register Configuration When CFS = 1
321
Figure 10.7 Output Waveform When DADR = H'0207 (os = 1)
322
Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
323
Usage Notes
324
Module Stop Mode Setting
324
Section 11 16-Bit Free-Running Timer (FRT)
325
Features
325
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
326
Input/Output Pins
327
Register Descriptions
327
Table 11.1 Pin Configuration
327
Free-Running Counter (FRC)
328
Input Capture Registers a to D (ICRA to ICRD)
328
Output Compare Registers a and B (OCRA and OCRB)
328
Output Compare Register DM (OCRDM)
329
Output Compare Registers AR and AF (OCRAR and OCRAF)
329
Timer Interrupt Enable Register (TIER)
330
Timer Control/Status Register (TCSR)
331
Timer Control Register (TCR)
334
Timer Output Compare Control Register (TOCR)
335
Operation
337
Pulse Output
337
Figure 11.2 Example of Pulse Output
337
Operation Timing
338
FRC Increment Timing
338
Figure 11.3 Increment Timing with Internal Clock Source
338
Figure 11.4 Increment Timing with External Clock Source
338
Output Compare Output Timing
339
FRC Clear Timing
339
Figure 11.5 Timing of Output Compare a Output
339
Figure 11.6 Clearing of FRC by Compare-Match a Signal
339
Input Capture Input Timing
340
Figure 11.7 Input Capture Input Signal Timing (Usual Case)
340
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read)
340
Buffered Input Capture Input Timing
341
Figure 11.9 Buffered Input Capture Timing
341
Timing of Input Capture Flag (ICF) Setting
342
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)
342
Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
342
Timing of Output Compare Flag (OCF) Setting
343
Timing of FRC Overflow Flag Setting
343
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
343
Automatic Addition Timing
344
Figure 11.13 Timing of Overflow Flag (OVF) Setting
344
Figure 11.14 OCRA Automatic Addition Timing
344
11.5.10 Mask Signal Generation Timing
345
Figure 11.15 Timing of Input Capture Mask Signal Setting
345
Figure 11.16 Timing of Input Capture Mask Signal Clearing
345
Interrupt Sources
346
Table 11.2 FRT Interrupt Sources
346
Usage Notes
347
Conflict between FRC Write and Clear
347
Figure 11.17 Conflict between FRC Write and Clear
347
Conflict between FRC Write and Increment
348
Figure 11.18 Conflict between FRC Write and Increment
348
Conflict between OCR Write and Compare-Match
349
Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used)
349
Switching of Internal Clock and FRC Operation
350
Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Used)
350
Table 11.3 Switching of Internal Clock and FRC Operation
351
Module Stop Mode Setting
352
Section 12 16-Bit Timer Pulse Unit (TPU)
353
Features
353
Figure 12.1 Block Diagram of TPU
354
Table 12.1 TPU Functions
355
Input/Output Pins
357
Table 12.2 Pin Configuration
357
Register Descriptions
358
Timer Control Register (TCR)
359
Table 12.3 CCLR2 to CCLR0 (Channel 0)
360
Table 12.4 CCLR2 to CCLR0 (Channels 1 and 2)
360
Table 12.5 TPSC2 to TPSC0 (Channel 0)
361
Table 12.6 TPSC2 to TPSC0 (Channel 1)
361
Table 12.7 TPSC2 to TPSC0 (Channel 2)
362
Timer Mode Register (TMDR)
363
Table 12.8 MD3 to MD0
364
Timer I/O Control Register (TIOR)
365
Table 12.9 TIORH_0 (Channel 0)
366
Table 12.10 TIORH_0 (Channel 0)
367
Table 12.11 TIORL_0 (Channel 0)
368
Table 12.12 TIORL_0 (Channel 0)
369
Table 12.13 TIOR_1 (Channel 1)
370
Table 12.14 TIOR_1 (Channel 1)
371
Table 12.15 TIOR_2 (Channel 2)
372
Table 12.16 TIOR_2 (Channel 2)
373
Timer Interrupt Enable Register (TIER)
374
Timer Status Register (TSR)
376
Timer Counter (TCNT)
379
Timer General Register (TGR)
379
Timer Start Register (TSTR)
379
Timer Synchro Register (TSYR)
380
Interface to Bus Master
381
16-Bit Registers
381
Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]
381
Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
382
Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
382
Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
382
Operation
383
Basic Functions
383
Figure 12.6 Example of Counter Operation Setting Procedure
383
Figure 12.7 Free-Running Counter Operation
384
Figure 12.8 Periodic Counter Operation
385
Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match
385
Figure 12.10 Example of 0 Output/1 Output Operation
386
Figure 12.11 Example of Toggle Output Operation
386
Figure 12.12 Example of Input Capture Operation Setting Procedure
387
Figure 12.13 Example of Input Capture Operation
388
Synchronous Operation
389
Figure 12.14 Example of Synchronous Operation Setting Procedure
389
Figure 12.15 Example of Synchronous Operation
390
Buffer Operation
391
Figure 12.16 Compare Match Buffer Operation
391
Figure 12.17 Input Capture Buffer Operation
391
Table 12.17 Register Combinations in Buffer Operation
391
Figure 12.18 Example of Buffer Operation Setting Procedure
392
Figure 12.19 Example of Buffer Operation (1)
393
Figure 12.20 Example of Buffer Operation (2)
394
PWM Modes
395
Figure 12.21 Example of PWM Mode Setting Procedure
396
Table 12.18 PWM Output Registers and Output Pins
396
Figure 12.22 Example of PWM Mode Operation (1)
397
Figure 12.23 Example of PWM Mode Operation (2)
398
Figure 12.24 Example of PWM Mode Operation (3)
399
Phase Counting Mode
400
Figure 12.25 Example of Phase Counting Mode Setting Procedure
400
Table 12.19 Phase Counting Mode Clock Input Pins
400
Figure 12.26 Example of Phase Counting Mode 1 Operation
401
Table 12.20 Up/Down-Count Conditions in Phase Counting Mode 1
401
Figure 12.27 Example of Phase Counting Mode 2 Operation
402
Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 2
402
Figure 12.28 Example of Phase Counting Mode 3 Operation
403
Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 3
403
Figure 12.29 Example of Phase Counting Mode 4 Operation
404
Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 4
404
Interrupts
405
Interrupt Source and Priority
405
Table 12.24 TPU Interrupts
406
DTC Activation
407
A/D Converter Activation
407
Operation Timing
408
Input/Output Timing
408
Figure 12.30 Count Timing in Internal Clock Operation
408
Figure 12.31 Count Timing in External Clock Operation
408
Figure 12.32 Output Compare Output Timing
409
Figure 12.33 Input Capture Input Signal Timing
409
Figure 12.34 Counter Clear Timing (Compare Match)
410
Figure 12.35 Counter Clear Timing (Input Capture)
410
Figure 12.36 Buffer Operation Timing (Compare Match)
411
Figure 12.37 Buffer Operation Timing (Input Capture)
411
Interrupt Signal Timing
412
Figure 12.38 TGI Interrupt Timing (Compare Match)
412
Figure 12.39 TGI Interrupt Timing (Input Capture)
413
Figure 12.40 TCIV Interrupt Setting Timing
414
Figure 12.41 TCIU Interrupt Setting Timing
414
Figure 12.42 Timing for Status Flag Clearing by CPU
415
Figure 12.43 Timing for Status Flag Clearing by DTC Activation
415
Usage Notes
416
Input Clock Restrictions
416
Caution on Period Setting
416
Figure 12.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
416
Conflict between TCNT Write and Clear Operations
417
Conflict between TCNT Write and Increment Operations
417
Figure 12.45 Conflict between TCNT Write and Clear Operations
417
Conflict between TGR Write and Compare Match
418
Figure 12.46 Conflict between TCNT Write and Increment Operations
418
Figure 12.47 Conflict between TGR Write and Compare Match
418
Conflict between Buffer Register Write and Compare Match
419
Figure 12.48 Conflict between Buffer Register Write and Compare Match
419
Conflict between TGR Read and Input Capture
420
Figure 12.49 Conflict between TGR Read and Input Capture
420
Conflict between TGR Write and Input Capture
421
Figure 12.50 Conflict between TGR Write and Input Capture
421
Conflict between Buffer Register Write and Input Capture
422
Figure 12.51 Conflict between Buffer Register Write and Input Capture
422
12.8.10 Conflict between Overflow/Underflow and Counter Clearing
423
Figure 12.52 Conflict between Overflow and Counter Clearing
423
12.8.11 Conflict between TCNT Write and Overflow/Underflow
424
12.8.12 Multiplexing of I/O Pins
424
12.8.13 Module Stop Mode Setting
424
Figure 12.53 Conflict between TCNT Write and Overflow
424
Section 13 8-Bit Timer (TMR)
425
Features
425
Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
428
Input/Output Pins
429
Table 13.1 Pin Configuration
429
Register Descriptions
430
Timer Counter (TCNT)
431
Time Constant Register a (TCORA)
431
Time Constant Register B (TCORB)
432
Timer Control Register (TCR)
432
Table 13.2 Clock Input to TCNT and Count Condition (1)
434
Table 13.2 Clock Input to TCNT and Count Condition (2)
435
Timer Control/Status Register (TCSR)
437
Time Constant Register C (TCORC)
442
Input Capture Registers R and F (TICRR and TICRF)
442
Timer Input Select Register (TISR)
443
Timer Connection Register I (TCONRI)
443
Timer Connection Register S (TCONRS)
444
Timer XY Control Register (TCRXY)
444
Table 13.3 Registers Accessible by TMR_X/TMR_Y
444
Operation
445
Pulse Output
445
Figure 13.3 Pulse Output Example
445
Operation Timing
446
TCNT Count Timing
446
Figure 13.4 Count Timing for Internal Clock Input
446
Figure 13.5 Count Timing for External Clock Input (both Edges)
446
Timing of CMFA and CMFB Setting at Compare-Match
447
Timing of Timer Output at Compare-Match
447
Figure 13.6 Timing of CMF Setting at Compare-Match
447
Figure 13.7 Timing of Toggled Timer Output by Compare-Match a Signal
447
Timing of Counter Clear at Compare-Match
448
TCNT External Reset Timing
448
Figure 13.8 Timing of Counter Clear by Compare-Match
448
Figure 13.9 Timing of Counter Clear by External Reset Input
448
Timing of Overflow Flag (OVF) Setting
449
Figure 13.10 Timing of OVF Flag Setting
449
TMR_0 and TMR_1 Cascaded Connection
450
16-Bit Count Mode
450
Compare-Match Count Mode
450
TMR_Y and TMR_X Cascaded Connection
451
16-Bit Count Mode
451
Compare-Match Count Mode
451
Input Capture Operation
452
Figure 13.11 Timing of Input Capture Operation
452
Figure 13.12 Timing of Input Capture Signal (Input Capture Signal Is Input During TICRR and TICRF Read)
453
Table 13.4 Input Capture Signal Selection
453
Interrupt Sources
454
Table 13.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X
454
Usage Notes
455
Conflict between TCNT Write and Counter Clear
455
Figure 13.13 Conflict between TCNT Write and Clear
455
Conflict between TCNT Write and Count-Up
456
Figure 13.14 Conflict between TCNT Write and Count-Up
456
Conflict between TCOR Write and Compare-Match
457
Figure 13.15 Conflict between TCOR Write and Compare-Match
457
Conflict between Compare-Matches a and B
458
Switching of Internal Clocks and TCNT Operation
458
Table 13.6 Timer Output Priorities
458
Table 13.7 Switching of Internal Clocks and TCNT Operation
459
Mode Setting with Cascaded Connection
460
Module Stop Mode Setting
460
Section 14 Watchdog Timer (WDT)
461
Features
461
Figure 14.1 Block Diagram of WDT
462
Input/Output Pins
463
Register Descriptions
463
Timer Counter (TCNT)
463
Table 14.1 Pin Configuration
463
Timer Control/Status Register (TCSR)
464
Operation
468
Watchdog Timer Mode
468
Interval Timer Mode
469
Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation
469
Figure 14.3 Interval Timer Mode Operation
469
RESO Signal Output Timing
470
Figure 14.4 OVF Flag Set Timing
470
Figure 14.5 Output Timing of RESO Signal
470
Interrupt Sources
471
Table 14.2 WDT Interrupt Source
471
Usage Notes
472
Notes on Register Access
472
Figure 14.6 Writing to TCNT and TCSR (WDT_0)
472
Conflict between Timer Counter (TCNT) Write and Increment
473
Figure 14.7 Conflict between TCNT Write and Increment
473
Changing Values of CKS2 to CKS0 Bits
474
Changing Value of PSS Bit
474
Switching between Watchdog Timer Mode and Interval Timer Mode
474
System Reset by RESO Signal
474
Figure 14.8 Sample Circuit for Resetting the System by the RESO Signal
474
Section 15 Serial Communication Interface (SCI, Irda)
475
Features
475
Figure 15.1 Block Diagram of SCI
477
Input/Output Pins
478
Table 15.1 Pin Configuration
478
Register Descriptions
479
Receive Shift Register (RSR)
479
Receive Data Register (RDR)
479
Transmit Data Register (TDR)
480
Transmit Shift Register (TSR)
480
Serial Mode Register (SMR)
480
Serial Control Register (SCR)
484
Serial Status Register (SSR)
487
Smart Card Mode Register (SCMR)
492
Bit Rate Register (BRR)
493
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
493
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
494
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
496
Table 15.4 Maximum Bit Rate for each Frequency (Asynchronous Mode)
498
Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
498
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
499
Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
500
Table 15.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, N = 0, S = 372)
500
Table 15.9 Maximum Bit Rate for each Frequency (Smart Card Interface Mode, S = 372)
500
Keyboard Comparator Control Register (KBCOMP)
501
Operation in Asynchronous Mode
503
Data Transfer Format
503
Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
503
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
504
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
505
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
505
Clock
506
Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)
506
SCI Initialization (Asynchronous Mode)
507
Figure 15.5 Sample SCI Initialization Flowchart
507
Serial Data Transmission (Asynchronous Mode)
508
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
508
Figure 15.7 Sample Serial Transmission Flowchart
509
Serial Data Reception (Asynchronous Mode)
510
Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
510
Table 15.11 SSR Status Flags and Receive Data Handling
511
Figure 15.9 Sample Serial Reception Flowchart (1)
512
Figure 15.9 Sample Serial Reception Flowchart (2)
513
Multiprocessor Communication Function
514
Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
515
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart
516
Multiprocessor Serial Data Transmission
516
Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
517
Multiprocessor Serial Data Reception
517
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
518
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)
519
Operation in Clocked Synchronous Mode
520
Clock
520
Figure 15.14 Data Format in Synchronous Communication (LSB-First)
520
SCI Initialization (Clocked Synchronous Mode)
521
Figure 15.15 Sample SCI Initialization Flowchart
521
Serial Data Transmission (Clocked Synchronous Mode)
522
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
523
Figure 15.17 Sample Serial Transmission Flowchart
524
Serial Data Reception (Clocked Synchronous Mode)
525
Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode
525
Figure 15.19 Sample Serial Reception Flowchart
526
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
527
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
528
Smart Card Interface Description
529
Sample Connection
529
Data Format (Except in Block Transfer Mode)
529
Figure 15.21 Pin Connection for Smart Card Interface
529
Figure 15.22 Data Formats in Normal Smart Card Interface Mode
530
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)
530
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)
530
Block Transfer Mode
531
Receive Data Sampling Timing and Reception Margin
531
Initialization
532
Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate)
532
Serial Data Transmission (Except in Block Transfer Mode)
533
Figure 15.26 Data Re-Transfer Operation in SCI Transmission Mode
534
Figure 15.27 TEND Flag Set Timings During Transmission
534
Figure 15.28 Sample Transmission Flowchart
535
Serial Data Reception (Except in Block Transfer Mode)
536
Figure 15.29 Data Re-Transfer Operation in SCI Reception Mode
536
Figure 15.30 Sample Reception Flowchart
537
Clock Output Control
538
Figure 15.31 Clock Output Fixing Timing
538
Figure 15.32 Clock Stop and Restart Procedure
539
Irda Operation
540
Figure 15.33 Irda Block Diagram
540
Figure 15.34 Irda Transmission and Reception
541
Table 15.12 Ircks2 to Ircks0 Bit Settings
543
Interrupt Sources
544
Interrupts in Normal Serial Communication Interface Mode
544
Table 15.13 SCI Interrupt Sources
544
Interrupts in Smart Card Interface Mode
545
Table 15.14 SCI Interrupt Sources
545
Usage Notes
546
15.10.1 Module Stop Mode Setting
546
15.10.2 Break Detection and Processing
546
15.10.3 Mark State and Break Sending
546
Receive Error Flags and Transmit Operations
546
(Clocked Synchronous Mode Only)
546
15.10.5 Relation between Writing to TDR and TDRE Flag
546
15.10.6 Restrictions on Using DTC
547
15.10.7 SCI Operations During Mode Transitions
547
Figure 15.35 Sample Transmission Using DTC in Clocked Synchronous Mode
547
Figure 15.36 Sample Flowchart for Mode Transition During Transmission
548
Figure 15.37 Pin States During Transmission in Asynchronous Mode (Internal Clock)
549
Figure 15.38 Pin States During Transmission in Clocked Synchronous Mode (Internal Clock)
549
Figure 15.39 Sample Flowchart for Mode Transition During Reception
550
15.10.8 Notes on Switching from SCK Pins to Port Pins
551
Figure 15.40 Switching from SCK Pins to Port Pins
551
Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
552
Section 16 I C Bus Interface (IIC)
553
Features
553
Figure 16.1 Block Diagram of I
555
Figure 16.2 I C Bus Interface Connections (Example: this LSI as Master)
556
Input/Output Pins
557
Table 16.1 Pin Configuration
557
Register Descriptions
558
C Bus Data Register (ICDR)
558
Slave Address Register (SAR)
559
Second Slave Address Register (SARX)
560
Table 16.2 Communication Format
561
C Bus Mode Register (ICMR)
562
Table 16.3 I 2 C Transfer Rate
564
C Bus Control Register (ICCR)
565
Table 16.4 Flags and Transfer States (Master Mode)
570
Table 16.5 Flags and Transfer States (Slave Mode)
572
C Bus Status Register (ICSR)
574
DDC Switch Register (DDCSWR)
578
C Bus Extended Control Register (ICXR)
579
Operation
583
C Bus Data Format
583
Figure 16.3 I C Bus Data Format (I C Bus Format)
583
Figure 16.4 I C Bus Data Format (Serial Format)
583
Figure 16.5 I C Bus Timing
584
Table 16.6 I 2 C Bus Data Format Symbols
584
Initialization
585
Master Transmit Operation
585
Figure 16.6 Sample Flowchart for IIC Initialization
585
Figure 16.7 Sample Flowchart for Operations in Master Transmit Mode
586
Figure 16.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
588
Master Receive Operation
589
Figure 16.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
589
Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
590
Figure 16.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
592
Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
592
Figure 16.13 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
594
Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1)
595
Figure 16.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1)
598
Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1)
598
Slave Receive Operation
599
Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
600
Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1)
602
Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1)
603
Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
604
Figure 16.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0)
606
Figure 16.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0)
606
Slave Transmit Operation
607
Figure 16.23 Sample Flowchart for Slave Transmit Mode
607
Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0)
609
IRIC Setting Timing and SCL Control
610
Figure 16.25 IRIC Setting Timing and SCL Control (1)
610
Figure 16.26 IRIC Setting Timing and SCL Control (2)
611
Figure 16.27 IRIC Setting Timing and SCL Control (3)
612
Operation by Using DTC
613
Table 16.7 Operation by Using DTC
614
Noise Canceller
615
Figure 16.28 Block Diagram of Noise Canceller
615
16.4.10 Initialization of Internal State
616
Interrupt Sources
617
Table 16.8 IIC Interrupt Sources
617
Usage Notes
618
Table 16.9 I 2 C Bus Timing (SCL and SDA Outputs)
618
Table 16.10 Permissible SCL Rise Time
619
Figure 16.29 Notes on Reading Master Receive Data
621
Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and
622
Figure 16.31 Stop Condition Issuance Timing
623
Figure 16.32 IRIC Flag Clearing Timing When WAIT = 1
624
Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode
625
Figure 16.34 TRS Bit Set Timing in Slave Mode
626
Figure 16.35 Diagram of Erroneous Operation When Arbitration Is Lost
628
Module Stop Mode Setting
628
Section 17 Keyboard Buffer Control Unit (KBU)
629
Features
629
Figure 17.1 Block Diagram of KBU
630
Figure 17.2 KBU Connection
631
Input/Output Pins
632
Table 17.1 Pin Configuration
632
Register Descriptions
633
Keyboard Control Register 1 (KBCR1)
633
Keyboard Buffer Control Register 2 (KBCR2)
635
Keyboard Control Register H (KBCRH)
636
Keyboard Control Register L (KBCRL)
638
Keyboard Data Buffer Register (KBBR)
640
Keyboard Buffer Transmit Data Register (KBTR)
640
Operation
641
Receive Operation
641
Figure 17.3 Sample Receive Processing Flowchart
642
Transmit Operation
643
Figure 17.4 Receive Timing
643
Figure 17.5 Sample Transmit Processing Flowchart
644
Receive Abort
645
Figure 17.6 Transmit Timing
645
Figure 17.7 (1) Sample Receive Abort Processing Flowchart
646
Figure 17.7 (2) Sample Receive Abort Processing Flowchart
647
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover)
647
KCLKI and KDI Read Timing
648
Figure 17.9 KCLKI and KDI Read Timing
648
KCLKO and KDO Write Timing
649
Figure 17.10 KCLKO and KDO Write Timing
649
KBF Setting Timing and KCLK Control
650
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing
650
Receive Timing
651
Figure 17.12 Receive Counter and KBBR Data Load Timing
651
Operation During Data Reception
652
Figure 17.13 Receive Timing and KCLK
652
KCLK Fall Interrupt Operation
653
Figure 17.14 Example of KCLK Input Fall Interrupt Operation
653
17.4.10 First KCLK Falling Interrupt
654
Figure 17.15 Timing of First KCLK Interrupt
654
Figure 17.16 First KCLK Interrupt Path
656
Figure 17.17 Interrupt Timing in Software Standby Mode, Watch Mode, and Subsleep Mode
657
Figure 17.18 Internal Flag of First KCLK Falling Interrupt in Software Standby Mode, Watch Mode, and Subsleep Mode
658
Usage Notes
659
KBIOE Setting and KCLK Falling Edge Detection
659
Figure 17.19 KBIOE Setting and KCLK Falling Edge Detection Timing
659
KD Output by KDO Bit (KBCRL) and by Automatic Transmission
660
Module Stop Mode Setting
660
Medium Speed Mode
660
Transmit Completion Flag (KBTE)
660
Figure 17.20 KDO Output
660
Section 18 LPC Interface (LPC)
661
Features
661
Figure 18.1 Block Diagram of LPC
663
Input/Output Pins
664
Table 18.1 Pin Configuration
664
Register Descriptions
665
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
667
Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
673
Host Interface Control Register 4 (HICR4)
676
LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)
677
LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)
679
Input Data Registers 1 to 4 (IDR1 to IDR4)
680
Output Data Registers 1 to 4 (ODR1 to ODR4)
681
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
681
Status Registers 1 to 4 (STR1 to STR4)
682
SERIRQ Control Register 0 (SIRQCR0)
688
SERIRQ Control Register 1 (SIRQCR1)
692
SERIRQ Control Register 2 (SIRQCR2)
697
Host Interface Select Register (HISEL)
701
RAM Buffer Address Register (RBUFAR)
702
Flash Memory Programming Address Registers H and L
703
(FLWARH and FLARL)
703
Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register (LMCDIDCR)
704
Erase Block Register (EBLKR)
705
LMC Status Registers 1 and 2 (LMCST1 and LMCST2)
706
LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2)
710
Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L)
713
Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L)
714
On-Chip RAM Host Base Address Registers H and L
715
(RAMBARH and RAMBARL)
715
Address Space Set Register (ASSR)
716
On-Chip RAM Address Space Set Register (RAMASSR)
717
Slave Address Register 1 (SAR1)
718
Slave Address Register 2 (SAR2)
719
On-Chip RAM Slave Address Register (RAMAR)
719
Flash Memory Write Protect Registers H, M, and L
720
(FWPRH, FWPRM, and FWPRL)
720
Flash Memory Read Protect Registers H, M, and L
722
(FRPRH, FRPRM, and FRPRL)
722
On-Chip RAM Protect Control Register (MPCR)
724
User Command Register (UCMDTR)
724
Operation
725
LPC Interface Activation
725
LPC I/O Cycles
725
Table 18.2 LPC I/O Cycle
726
Figure 18.2 Typical LFRAME Timing
727
Figure 18.3 Abort Mechanism
727
Gate A20
728
Table 18.3 GA20 (P81) Setting/Clearing Timing
728
Figure 18.4 GA20 Output
729
Table 18.4 Fast Gate A20 Output Signals
730
LPC Interface Shutdown Function (LPCPD)
731
Table 18.5 Scope of LPC Interface Pin Shutdown
732
Table 18.6 Scope of Initialization in each LPC Interface Mode
733
Figure 18.5 Power-Down State Termination Timing
734
LPC Interface Serialized Interrupt Operation (SERIRQ)
735
Figure 18.6 SERIRQ Timing
735
Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration
736
LPC Interface Clock Start Request
737
LPC/FW Memory Cycle
737
Figure 18.7 Clock Start Request Timing
737
Table 18.8 LPC Memory Cycle
738
Table 18.9 FW Memory Cycle (Byte Transfer)
739
LPC/FW Memory Access Command
740
Figure 18.8 Example of Command Space Setting
740
Table 18.10 List of LPC/FW Memory Access Commands
741
Table 18.11 List of Factors that Prevents SYNC Field Being Sent Back
745
Flash Memory Address Translation (Host → Slave)
748
Figure 18.9 Example of Flash Memory Address Translation
748
On-Chip RAM Address Translation (Host → Slave)
749
Figure 18.10 Example of On-Chip RAM Address Translation
749
18.4.11 Address Space Priority
750
18.4.12 Example 1 of Address Space Priority
751
Figure 18.11 Example 1 of Address Space Priority
751
18.4.13 Example 2 of Address Space Priority
752
Figure 18.12 Example 2 of Address Space Priority
752
18.4.14 Flash Memory Protection
753
Figure 18.13 Flash Memory Protection
754
18.4.15 On-Chip RAM Protection
755
18.4.16 Flash Memory Programming
755
Figure 18.14 Protected Address Space in On-Chip RAM
755
Figure 18.15 Example of Programming Flash Memory
756
18.4.17 Flash Memory Erasing
757
Figure 18.16 Example of Erasing Flash Memory
757
Interrupt Sources
758
IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI
758
Table 18.12 Receive Complete Interrupts and Error Interrupt
758
SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12
759
Table 18.13 HIRQ Setting and Clearing Conditions
760
Figure 18.17 HIRQ Flowchart (Example of Channel 1)
761
Usage Note
762
Data Conflict
762
Module Stop Mode Setting
763
Operating Mode in LPC/FW Memory Write Cycle
763
Table 18.14 Host Address Example
763
Section 19 A/D Converter
765
Features
765
Figure 19.1 Block Diagram of A/D Converter
766
Input/Output Pins
767
Table 19.1 Pin Configuration
767
Register Descriptions
768
A/D Data Registers a to D (ADDRA to ADDRD)
768
Table 19.2 Analog Input Channels and Corresponding ADDR
768
A/D Control/Status Register (ADCSR)
769
A/D Control Register (ADCR)
770
Operation
771
Single Mode
771
Scan Mode
771
Input Sampling and A/D Conversion Time
772
Figure 19.2 A/D Conversion Timing
773
External Trigger Input Timing
774
Figure 19.3 External Trigger Input Timing
774
Table 19.3 A/D Conversion Time (Single Mode)
774
Interrupt Source
775
A/D Conversion Accuracy Definitions
775
Table 19.4 A/D Converter Interrupt Source
775
Figure 19.4 A/D Conversion Accuracy Definitions
776
Figure 19.5 A/D Conversion Accuracy Definitions
776
Usage Notes
777
Permissible Signal Source Impedance
777
Influences on Absolute Accuracy
777
Figure 19.6 Example of Analog Input Circuit
777
Setting Range of Analog Power Supply and Other Pins
778
Notes on Board Design
778
Notes on Noise Countermeasures
778
Module Stop Mode Setting
779
Figure 19.7 Example of Analog Input Protection Circuit
779
Figure 19.8 Analog Input Pin Equivalent Circuit
779
Section 20 RAM
781
Section 21 Flash Memory (0.18-ΜM F-ZTAT Version)
783
Features
783
Figure 21.1 Block Diagram of Flash Memory
784
User Boot Mode
784
Figure 21.2 Mode Transition for Flash Memory
785
Mode Transitions
785
Mode Comparison
786
Table 21.1 Comparison of Programming Modes
786
Block Division
787
Figure 21.3 Flash Memory Configuration
787
Flash Memory MAT Configuration
787
Figure 21.4 Block Division of User MAT (1)
788
Figure 21.4 Block Division of User MAT (2)
789
Figure 21.5 Overview of User Procedure Program
790
Programming/Erasing Interface
790
Input/Output Pins
792
Register Descriptions
792
Table 21.2 Pin Configuration
792
Table 21.3 Register/Parameter and Target Mode
793
Programming/Erasing Interface Registers
794
Programming/Erasing Interface Parameters
801
Table 21.4 Parameters and Target Modes
802
On-Board Programming
812
Boot Mode
812
Table 21.5 On-Board Programming Mode Setting
812
Figure 21.6 System Configuration in Boot Mode
813
Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI
813
Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by this LSI
814
Figure 21.8 Overview of Boot Mode State Transition Diagram
815
User Program Mode
816
Figure 21.9 Programming/Erasing Overview Flow
816
Figure 21.10 RAM Map When Programming/Erasing Is Executed
817
Figure 21.11 Programming Procedure
818
Figure 21.12 Erasing Procedure
824
Figure 21.13 Repeating Procedure of Erasing and Programming
826
User Boot Mode
827
Figure 21.14 Procedure for Programming User MAT in User Boot Mode
828
Figure 21.15 Procedure for Erasing User MAT in User Boot Mode
830
Storable Areas for Procedure Program and Program Data
831
Table 21.7 Executable MAT
832
Table 21.8 (1) Usable Area for Programming in User Program Mode
833
Table 21.8 (2) Usable Area for Erasure in User Program Mode
835
Table 21.8 (3) Usable Area for Programming in User Boot Mode
836
Table 21.8 (4) Usable Area for Erasure in User Boot Mode
838
Protection
839
Hardware Protection
839
Table 21.9 Hardware Protection
840
Software Protection
841
Error Protection
841
Table 21.10 Software Protection
841
Figure 21.16 Transitions to Error-Protection State
842
Switching between User MAT and User Boot MAT
843
Figure 21.17 Switching between User MAT and User Boot MAT
843
Programmer Mode
844
Figure 21.18 Memory Map in Programmer Mode
844
Serial Communication Interface Specifications for Boot Mode
845
Figure 21.19 Boot Program States
846
Figure 21.20 Bit-Rate-Adjustment Sequence
847
Figure 21.21 Communication Protocol Format
848
Table 21.11 Inquiry and Selection Commands
849
Figure 21.22 Sequence of New Bit Rate Selection
859
Table 21.12 Programming/Erasing Commands
861
Figure 21.23 Programming Sequence
862
Figure 21.24 Erasure Sequence
866
Table 21.13 Status Code
871
Table 21.14 Error Code
871
Usage Notes
872
Section 22 Boundary Scan (JTAG)
875
Features
875
Figure 22.1 JTAG Block Diagram
876
Input/Output Pins
877
Table 22.1 Pin Configuration
877
Register Descriptions
878
Instruction Register (SDIR)
878
Table 22.2 JTAG Register Serial Transfer
878
Bypass Register (SDBPR)
880
Boundary Scan Register (SDBSR)
880
Table 22.3 Correspondence between Pins and Boundary Scan Register
880
ID Code Register (SDIDR)
890
Operation
890
TAP Controller State Transitions
890
JTAG Reset
891
Figure 22.2 TAP Controller State Transitions
891
Boundary Scan
892
Supported Instructions
892
Notes
894
Usage Notes
894
Figure 22.3 Reset Signal Circuit Without Reset Signal Interference
895
Figure 22.4 Serial Data Input/Output (1)
896
Figure 22.5 Serial Data Input/Output (2)
896
Section 23 Clock Pulse Generator
897
Figure 23.1 Block Diagram of Clock Pulse Generator
897
Oscillator
898
Connecting Crystal Resonator
898
Figure 23.2 Typical Connection to Crystal Resonator
898
Figure 23.3 Equivalent Circuit of Crystal Resonator
898
Table 23.1 Damping Resistor Values
898
External Clock Input Method
899
Figure 23.4 Example of External Clock Input
899
Table 23.2 Crystal Resonator Parameters
899
Figure 23.5 External Clock Input Timing
900
Table 23.3 External Clock Input Conditions
900
Figure 23.6 Timing of External Clock Output Stabilization Delay Time
901
Table 23.4 External Clock Output Stabilization Delay Time
901
Duty Correction Circuit
902
Medium-Speed Clock Divider
902
Bus Master Clock Select Circuit
902
Subclock Input Circuit
903
Figure 23.7 Subclock Input from EXCL Pin and Exexcl Pin
903
Table 23.5 Subclock Input Conditions
903
Subclock Waveform Forming Circuit
904
Clock Select Circuit
904
Figure 23.8 Subclock Input Timing
904
Handling of X1 and X2 Pins
905
Usage Notes
905
Notes on Resonator
905
Notes on Board Design
905
Figure 23.9 Handling of X1 and X2 Pins
905
Figure 23.10 Note on Board Design of Oscillator Section
905
Section 24 Power-Down Modes
907
Register Descriptions
908
Standby Control Register (SBYCR)
908
Low-Power Control Register (LPWRCR)
910
Table 24.1 Operating Frequency and Wait Time
910
Module Stop Control Registers H, L, and a (MSTPCRH, MSTPCRL, MSTPCRA)
912
Mode Transitions and LSI States
914
Figure 24.1 Mode Transition Diagram
915
Table 24.2 LSI Internal States in each Operating Mode
916
Medium-Speed Mode
918
Sleep Mode
919
Figure 24.2 Medium-Speed Mode Timing
919
Software Standby Mode
920
Figure 24.3 Software Standby Mode Application Example
921
Hardware Standby Mode
922
Figure 24.4 Hardware Standby Mode Timing
922
Watch Mode
923
Subsleep Mode
924
Subactive Mode
925
Module Stop Mode
926
Direct Transitions
926
Usage Notes
927
24.12.1 I/O Port Status
927
24.12.2 Current Consumption When Waiting for Oscillation Stabilization
927
24.12.3 DTC Module Stop Mode
927
Section 25 List of Registers
929
Register Addresses (Address Order)
931
Register Bits
945
Register States in each Operating Mode
957
Register Selection Condition
968
Register Addresses (Classification by Type of Module)
981
Section 26 Electrical Characteristics
995
Absolute Maximum Ratings
995
Table 26.1 Absolute Maximum Ratings
995
DC Characteristics
996
Table 26.2 DC Characteristics (1)
996
Table 26.2 DC Characteristics (2)
998
Table 26.2 DC Characteristics (3) Using LPC Function
999
Table 26.3 Permissible Output Currents
1000
Table 26.4 Bus Drive Characteristics
1001
Figure 26.1 Darlington Transistor Drive Circuit (Example)
1002
Figure 26.2 LED Drive Circuit (Example)
1002
AC Characteristics
1003
Figure 26.3 Output Load Circuit
1003
Clock Timing
1004
Figure 26.4 System Clock Timing
1004
Table 26.5 Clock Timing
1004
Figure 26.5 Oscillation Stabilization Timing
1005
Figure 26.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)
1005
Control Signal Timing
1006
Figure 26.7 Reset Input Timing
1006
Table 26.6 Control Signal Timing
1006
Figure 26.8 Interrupt Input Timing
1007
Timing of On-Chip Peripheral Modules
1007
Table 26.7 Timing of On-Chip Peripheral Modules
1008
Figure 26.10 FRT Input/Output Timing
1009
Figure 26.11 FRT Clock Input Timing
1009
Figure 26.9 I/O Port Input/Output Timing
1009
Figure 26.12 TPU Input/Output Timing
1010
Figure 26.13 TPU Clock Input Timing
1010
Figure 26.14 8-Bit Timer Output Timing
1010
Figure 26.15 8-Bit Timer Clock Input Timing
1010
Figure 26.16 8-Bit Timer Reset Input Timing
1011
Figure 26.17 PWM, PWMX Output Timing
1011
Figure 26.18 SCK Clock Input Timing
1011
Figure 26.19 SCI Input/Output Timing (Clock Synchronous Mode)
1011
Figure 26.20 A/D Converter External Trigger Input Timing
1012
Figure 26.21 WDT Output Timing (RESO)
1012
Table 26.8 KBU Bus Timing
1012
Figure 26.22 Keyboard Buffer Control Unit Timing
1013
Table 26.9 I 2 C Bus Timing
1014
Figure 26.23 I C Bus Interface Input/Output Timing
1015
Table 26.10 LPC Timing
1015
Figure 26.24 LPC Interface Timing
1016
Figure 26.25 Test Conditions for Tester
1016
Figure 26.26 JTAG ETCK Timing
1017
Table 26.11 JTAG Timing
1017
Figure 26.27 Reset Hold Timing
1018
Figure 26.28 JTAG Input/Output Timing
1018
A/D Conversion Characteristics
1019
Table 26.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion)
1019
Flash Memory Characteristics
1020
Table 26.13 Flash Memory Characteristics
1020
Usage Notes
1021
Figure 26.29 Connection of VCL Capacitor
1021
Appendix
1023
I/O Port States in each Pin State
1023
Table A.1 I/O Port States in each Pin State
1023
Product Lineup
1024
Package Dimensions
1025
Figure C.1 Package Dimensions (TFP-144)
1025
Index
1027
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