5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Pin Configuration
Symbol
NMI
IRQ15 to IRQ0,
ExIRQ15 to ExIRQ0
KIN15 to KIN0
WUE15 to WUE8
WUE7 to WUE0
I/O
Function
Input
Nonmaskable external interrupt pin
Rising edge or falling edge can be selected
Input
Maskable external interrupt pins
Rising-edge, falling-edge, or both-edge detection, or level-
sensing, can be selected individually for each pin. To which
pin the IRQ15 to IRQ0 interrupt is input can be selected from
the IRQn and ExIRQn pins. (n = 15 to 0)
Input
Maskable external interrupt pins
When EIVS = 0, falling-edge or level-sensing can be selected.
When EIVS = 1, an interrupt is requested at the falling edge.
Input
Maskable external interrupt pins
An interrupt is requested at the falling edge.
Input
Maskable external interrupt pins
When EIVS = 0, falling-edge or level-sensing can be selected.
When EIVS = 1, an interrupt is requested at the falling edge.
Section 5 Interrupt Controller
Rev. 3.00 Jul. 14, 2005 Page 81 of 986
REJ09B0098-0300