Usage Notes; Conflict Between Tcnt Write And Counter Clear; Figure 13.13 Conflict Between Tcnt Write And Clear - Renesas H8S Series Hardware Manual

13.9

Usage Notes

13.9.1

Conflict between TCNT Write and Counter Clear

If a counter clear signal is generated during the T
13.13, clearing takes priority and the counter write is not performed.
φ
Address
Internal write signal
Counter clear signal
TCNT

Figure 13.13 Conflict between TCNT Write and Clear

state of a TCNT write cycle as shown in figure
2
TCNT write cycle by CPU
T 1 T 2
TCNT address
N
Section 13 8-Bit Timer (TMR)
H'00
Rev. 3.00 Jul. 14, 2005 Page 407 of 986
REJ09B0098-0300