Figure 16.34 Trs Bit Set Timing In Slave Mode - Renesas H8S Series Hardware Manual

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Section 16 I C Bus Interface (IIC)
12. Note on TRS bit setting in slave mode
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In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 16.34), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 16.34), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 16.34. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
SDA
8 9
SCL
Data
TRS
transmission
TRS bit setting
The rise of the 9th clock is detected
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Rev. 3.00 Jul. 14, 2005 Page 578 of 986
REJ09B0098-0300
Restart condition
(a)
1
Address reception
TRS bit setting is suspended in this period
ICDR dummy read

Figure 16.34 TRS Bit Set Timing in Slave Mode

(b)
2 3 4 5 6
A
7 8 9
The rise of the 9th clock is detected