10.9.11 Contention Between Overflow/Underflow And Counter Clearing; Figure 10.52 Contention Between Overflow And Counter Clearing - Renesas H8S Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)

10.9.11 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
TCNT input
clock
TCNT
Counter
clear signal
TGF
TCFV

Figure 10.52 Contention between Overflow and Counter Clearing

Rev. 6.00 Mar 15, 2006 page 242 of 570
REJ09B0211-0600
φ
H'FFFF
Prohibited
H'0000