Figure 16.32 Iric Flag Clearing Timing When Wait = 1 - Renesas H8S Series Hardware Manual

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Section 16 I C Bus Interface (IIC)
10. Note on IRIC flag clear when the wait function is used
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
SCL
SDA
IRIC

Figure 16.32 IRIC Flag Clearing Timing when WAIT = 1

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Rev. 3.00 Jul. 14, 2005 Page 576 of 986
REJ09B0098-0300
Secures a high period
VIH
SCL = low detected
[1] SCL = low determination
[2] IRIC clear
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C bust interface