Noise Canceller Enable Register; Noise Canceller Mode Control Register - Renesas H8S Series Hardware Manual

8.16.4 Noise Canceller Enable Register (PGNCE)
PGNCE enables or disables the noise cancel circuit at port G. To use the port G pins as the IIC_0
and IIC_1input/output pins, these bits in PGNCE should be disabled.
Bit Bit Name
7 PG7NCE
6 PG6NCE
5 PG5NCE
4 PG4NCE
3 PG3NCE
2 PG2NCE
1 PG1NCE
0 PG0NCE
8.16.5 Noise Canceller Mode Control Register (PGNCMC)
PGNCMC controls whether 1 or 0 is expected for the input signal to port G in bit units.
Bit Bit Name
7 PG7NCMC
6 PG6NCMC
5 PG5NCMC
4 PG4NCMC
3 PG3NCMC
2 PG2NCMC
1 PG1NCMC
0 PG0NCMC
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Noise cancel circuit is enabled when PGNCE bit is
set to 1, and the pin state is fetched in the PGPIN
in the sampling cycle set by the PGNCCS.
Description
1 expected: 1 is stored in the port data register
when 1 is input
0 expected: 0 is stored in the port data register
when 0 is input
Rev. 3.00 Jul. 14, 2005 Page 235 of 986
Section 8 I/O Ports
REJ09B0098-0300