Renesas H8S Series Hardware Manual page 140

Section 5 Interrupt Controller
• ISR
Bit Bit Name
7 IRQ7F
6 IRQ6F
5 IRQ5F
4 IRQ4F
3 IRQ3F
2 IRQ2F
1 IRQ1F
0 IRQ0F
Note: Only 0 can be written for clearing the flag.
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Rev. 3.00 Jul. 14, 2005 Page 92 of 986
REJ09B0098-0300
Initial Value R/W
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
Description
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
•
When writing 0 to IRQnF flag after reading
IRQnF = 1
•
When interrupt exception handling is executed
when low-level detection is set and IRQn or
ExIRQn input is high
•
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 7 to 0)
Note: The IRQn or ExIRQn pin is selected by the
IRQ sense port select register (ISSR).