Conflict Between Timer Counter (Tcnt) Write And Increment; Changing Values Of Cks2 To Cks0 Bits; Switching Between Watchdog Timer Mode And Interval Timer Mode; Figure 15.7 Conflict Between Tcnt Write And Increment - Renesas H8S/2158 User Manual

Section 15 Watchdog Timer (WDT)
15.6.2

Conflict between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 15.7 shows this operation.
φ
Address
Internal write signal
TCNT input clock
TCNT

Figure 15.7 Conflict between TCNT Write and Increment

15.6.3

Changing Values of CKS2 to CKS0 Bits

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
15.6.4

Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
Rev. 3.00 Jan 25, 2006 page 384 of 872
REJ09B0286-0300
TCNT write cycle
T 1 T 2
N
Counter write data
M