Renesas H8S Series Hardware Manual page 33

Figure 10.3 PWMX (D/A) Operation ......................................................................................... 269
Figure 10.4 Output Waveform (OS = 0, DADR corresponds to T
Figure 10.5 Output Waveform (OS = 1, DADR corresponds to T
Figure 10.6 D/A Data Register Configuration when CFS = 1 .................................................... 273
Figure 10.7 Output Waveform when DADR = H'0207 (OS = 1) ............................................... 274
Section 11 16-Bit Free-Running Timer (FRT)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer ....................................................... 278
Figure 11.2 Example of Pulse Output......................................................................................... 289
Figure 11.3 Increment Timing with Internal Clock Source ........................................................ 290
Figure 11.4 Increment Timing with External Clock Source ....................................................... 290
Figure 11.5 Timing of Output Compare A Output ..................................................................... 291
Figure 11.6 Clearing of FRC by Compare-Match A Signal ....................................................... 291
Figure 11.7 Input Capture Input Signal Timing (Usual Case) .................................................... 292
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)....................... 292
Figure 11.9 Buffered Input Capture Timing ............................................................................... 293
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) ...................................................... 294
Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting .................. 294
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................. 295
Figure 11.13 Timing of Overflow Flag (OVF) Setting............................................................... 296
Figure 11.14 OCRA Automatic Addition Timing ...................................................................... 296
Figure 11.15 Timing of Input Capture Mask Signal Setting....................................................... 297
Figure 11.16 Timing of Input Capture Mask Signal Clearing .................................................... 297
Figure 11.17 Conflict between FRC Write and Clear................................................................. 299
Figure 11.18 Conflict between FRC Write and Increment ......................................................... 300
Figure 11.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) ............................................... 301
Figure 11.20 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used) ...................................................... 302
Section 12 16-Bit Timer Pulse Unit (TPU)
Figure 12.1 Block Diagram of TPU............................................................................................ 306
Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 333
Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 334
Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)].............. 334
Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] ....... 334
Figure 12.6 Example of Counter Operation Setting Procedure .................................................. 335
Figure 12.7 Free-Running Counter Operation ............................................................................ 336
Figure 12.8 Periodic Counter Operation..................................................................................... 337
Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match.............. 337
Figure 12.10 Example of 0 Output/1 Output Operation ............................................................. 338
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Rev. 3.00 Jul. 14, 2005 Page xxxiii of xlviii