Operation By Using Dtc - Renesas H8S Series Hardware Manual

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Section 16 I C Bus Interface (IIC)
16.4.8

Operation by Using DTC

This LSI provides the DTC to allow consecutive transfer. The DTC is activated when the IRTR
flag which is one of two interrupt flags (IRIC and IRTR) is set to 1. When the ACKE bit is cleared
to 0, regardless of the acknowledge bit, the ICDRE, IRIC, and IRTR flags are set at the
completion of the data transfer. When the ACKE bit is set to 1, if data transmission has been
completed with the acknowledge bit of 0, the ICDRE, IRIC, and IRTR flags are set. When the
ACKE bit is set to 1, if data transmission has been completed with the acknowledge bit of 1, only
the IRIC flag is set.
When the DTC is activated, the ICDRE, IRIC, and IRTR flags are cleared to 0 after required
transfers has been performed. Therefore, any interrupt is occurred while data is transferred
continuously. However, when the ACKE bit is set to 1, if the data transmission has been
completed with the acknowledge bit of 1, the DTC is not be activated and an interrupt is occurred
if enabled.
According to the reception device, the acknowledge bit indicates the completion of receive data
processing or is fixed to 1 without any indication.
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In the I C bus format, the selection of a slave device and transfer direction by the slave address
and R/W bit, and confirming reception and indicating the last frame by the acknowledge bit are
performed. Therefore, the consecutive data transfer by the DTC should be executed with the
processing of CPU by interrupts.
Table 16.7 shows the sample processing by using the DTC. It is supposed that the number of
transfer data has been known in the slave mode.
Rev. 3.00 Jul. 14, 2005 Page 565 of 986
REJ09B0098-0300