Serirq Control Register 1 (Sirqcr1) - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)

18.3.11 SERIRQ Control Register 1 (SIRQCR1)

SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
Bit Bit Name Initial Value Slave Host Description
7 IRQ11E3 0
Rev. 3.00 Jul. 14, 2005 Page 644 of 986
REJ09B0098-0300
R/W

R/W Host IRQ11 Interrupt Enable 3
Enables or disables an HIRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ11 interrupt request by OBF3A and
IRQE11E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ11 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ11E3 = 0