Renesas H8S Series Hardware Manual page 48

Table 21.14 Error Code ........................................................................................................ 823
Section 22 Boundary Scan (JTAG)
Table 22.1 Pin Configuration.................................................................................................. 829
Table 22.2 JTAG Register Serial Transfer.............................................................................. 830
Table 22.3 Correspondence between Pins and Boundary Scan Register ................................ 832
Section 23 Clock Pulse Generator
Table 23.1 Damping Resistor Values ..................................................................................... 850
Table 23.2 Crystal Resonator Parameters ............................................................................... 851
Table 23.3 External Clock Input Conditions .......................................................................... 852
Table 23.4 External Clock Output Stabilization Delay Time ................................................. 853
Table 23.5 Subclock Input Conditions.................................................................................... 855
Section 24 Power-Down Modes
Table 24.1 Operating Frequency and Wait Time.................................................................... 862
Table 24.2 LSI Internal States in Each Operating Mode ........................................................ 868
Section 26 Electrical Characteristics
Table 26.1 Absolute Maximum Ratings ................................................................................. 947
Table 26.2 DC Characteristics (1) .......................................................................................... 948
Table 26.2 DC Characteristics (2) .......................................................................................... 950
Table 26.2 DC Characteristics (3) Using LPC Function......................................................... 951
Table 26.3 Permissible Output Currents................................................................................. 952
Table 26.4 Bus Drive Characteristics ..................................................................................... 953
Table 26.5 Clock Timing ........................................................................................................ 956
Table 26.6 Control Signal Timing .......................................................................................... 958
Table 26.7 Timing of On-Chip Peripheral Modules ............................................................... 960
Table 26.8 KBU Bus Timing.................................................................................................. 964
2
Table 26.9 I C Bus Timing ..................................................................................................... 966
Table 26.10 LPC Timing ...................................................................................................... 967
Table 26.11 JTAG Timing.................................................................................................... 969
Table 26.12 A/D Conversion Characteristics
(AN7 to AN0 Input: 134/266-State Conversion) .............................................. 971
Table 26.13 Flash Memory Characteristics .......................................................................... 972
Appendix
Table A.1 I/O Port States in Each Pin State........................................................................... 975
Rev. 3.00 Jul. 14, 2005 Page xlviii of xlviii