Figure 5.5 Block Diagram Of Interrupts Kin15 To Kin0 And Wue15 To Wue0 (Example Of Wue15 To Wue8) - Renesas H8S Series Hardware Manual

• Extended vector mode (EIVS = 1 in SYSCR3)
 Interrupts KIN15 to KIN8, KIN7 to KIN0, WUE15 to WUE8, and WUE7 to WUE0 each
form a group. The interrupt exception handling for an interrupt request from the same
group is started at the same vector address.
 An interrupt request is generated by a falling edge at pins KIN15 to KIN0 and WUE15 to
WUE0.
 Enabling or disabling of interrupt requests KIN15 to KIN0 and WUE15 to WUE0 can be
selected using KMIMRA, KMIMR, WUEMRB, and WUEMR.
 The status of interrupt requests KIN15 to KIN0 and WUE15 to WUE0 are not indicated.
 An IRQ6 interrupt is enabled only by input to the ExIRQ6 pin. The IRQ6 pin is only
available for a KIN interrupt input, and functions as the KIN6 pin. The initial value of the
KMIMR6 bit is 1. For the IRQ7 interrupt, either the IRQ7 pin or ExIRQ7 pin can be
selected as the input pin using the ISS7 bit. The IRQ7 interrupt is not affected by the
settings of the KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 bits.
The detection of interrupts KIN15 to KIN0 and WUE15 to WUE0 does not depend on whether the
relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt
input pin, clear the DDR bit of the corresponding port to 0 so it is not used as an I/O pin for
another function.
A block diagram of interrupts KIN15 to KIN0 and WUE15 to WUE0 is shown in figure 5.5.
WUEMRn
WUEn input
n = 15 to 8
Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0
Falling-edge
detection circuit
Clear signal
(Example of WUE15 to WUE8)
Section 5 Interrupt Controller
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Rev. 3.00 Jul. 14, 2005 Page 101 of 986
WUEn interrupt request
REJ09B0098-0300