Renesas H8S Series Hardware Manual page 40

Figure 21.18 Memory Map in Programmer Mode...................................................................... 796
Figure 21.19 Boot Program States.............................................................................................. 798
Figure 21.20 Bit-Rate-Adjustment Sequence ............................................................................. 799
Figure 21.21 Communication Protocol Format .......................................................................... 800
Figure 21.22 Sequence of New Bit Rate Selection..................................................................... 811
Figure 21.23 Programming Sequence......................................................................................... 814
Figure 21.24 Erasure Sequence .................................................................................................. 818
Section 22 Boundary Scan (JTAG)
Figure 22.1 JTAG Block Diagram.............................................................................................. 828
Figure 22.2 TAP Controller State Transitions ............................................................................ 843
Figure 22.3 Reset Signal Circuit without Reset Signal Interference .......................................... 847
Figure 22.4 Serial Data Input/Output (1).................................................................................... 848
Figure 22.5 Serial Data Input/Output (2).................................................................................... 848
Section 23 Clock Pulse Generator
Figure 23.1 Block Diagram of Clock Pulse Generator ............................................................... 849
Figure 23.2 Typical Connection to Crystal Resonator................................................................ 850
Figure 23.3 Equivalent Circuit of Crystal Resonator.................................................................. 850
Figure 23.4 Example of External Clock Input ............................................................................ 851
Figure 23.5 External Clock Input Timing................................................................................... 852
Figure 23.6 Timing of External Clock Output Stabilization Delay Time................................... 853
Figure 23.7 Subclock Input from EXCL Pin and ExEXCL Pin ................................................. 855
Figure 23.8 Subclock Input Timing............................................................................................ 856
Figure 23.9 Handling of X1 and X2 Pins ................................................................................... 857
Figure 23.10 Note on Board Design of Oscillator Section ......................................................... 857
Section 24 Power-Down Modes
Figure 24.1 Mode Transition Diagram ....................................................................................... 867
Figure 24.2 Medium-Speed Mode Timing ................................................................................. 871
Figure 24.3 Software Standby Mode Application Example ....................................................... 873
Figure 24.4 Hardware Standby Mode Timing ............................................................................ 874
Section 26 Electrical Characteristics
Figure 26.1 Darlington Transistor Drive Circuit (Example)....................................................... 954
Figure 26.2 LED Drive Circuit (Example) ................................................................................. 954
Figure 26.3 Output Load Circuit ................................................................................................ 955
Figure 26.4 System Clock Timing.............................................................................................. 956
Figure 26.5 Oscillation Stabilization Timing.............................................................................. 957
Figure 26.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 957
Figure 26.7 Reset Input Timing.................................................................................................. 958
Figure 26.8 Interrupt Input Timing............................................................................................. 959
Rev. 3.00 Jul. 14, 2005 Page xl of xlviii