Storable Areas For Procedure Program And Program Data - Renesas H8S Series Hardware Manual

The difference between the erasing procedures in user program mode and user boot mode depends
on whether the MAT is switched or not as shown in figure 21.15.
MAT switching is enabled by writing a specific value to FMATS. Note however that while the
MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until
MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is
read is undetermined. Perform MAT switching in accordance with the description in section 21.6,
Switching between User MAT and User Boot MAT.
Except for MAT switching, the erasing procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM and user
MAT) is shown in section 21.4.4, Storable Areas for Procedure Program and Program Data.
21.4.4

Storable Areas for Procedure Program and Program Data

In the descriptions in the previous section, the storable areas for the programming/erasing
procedure programs and program data are assumed to be in the on-chip RAM. However, the
procedure programs and program data can be stored in and executed from other areas, such as part
of flash memory which is not to be programmed or erased.
(1) Conditions that Apply to Programming/Erasing
1. The on-chip programming/erasing program is downloaded from the address in the on-chip
RAM specified by FTDAR, therefore, this area is not available for use.
2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So,
make sure that this area is allocated.
3. Download by setting the SCO bit to 1 will lead to switching of the MATs. Therefore, if this
operation is used, it should be executed from the on-chip RAM.
4. The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been determined. The required procedure programs, NMI handling
vector, and NMI handling routine should be transferred to the on-chip RAM before
programming/erasing of the flash memory starts.
5. Since flash memory is not accessible during programming/erasing processing, programs
downloaded to the on-chip RAM are executed. The procedure programs that initiate
programming/erasing processing, and execution areas for the NMI interrupt vector table and
NMI interrupt handling program must be stored in on-chip RAM.
Section 21 Flash Memory (0.18-µm F-ZTAT Version)
Rev. 3.00 Jul. 14, 2005 Page 783 of 986
REJ09B0098-0300