Flash Memory Programming Address Registers H And L; (Flwarh And Flarl) - Renesas H8S Series Hardware Manual

18.3.15 Flash Memory Programming Address Registers H and L (FLWARH and FLARL)
FLWAR stores the start address of the flash memory programming in an LPC/FW memory cycle.
Bits 19 to 7 of the start address set by the FLWAR set command are stored in this register. Bits 23
to 20 of the address are fixed H'0, and 6 to 0 are fixed H'00.
• FLWARH
Bit Bit Name Initial Value Slave Host Description
7 to 5 
All 0
4 FWA19 0
3 FWA18 0
2 FWA17 0
1 FWA16 0
0
FWA15 0
Note: Can be written to by the FLWAR set command.
*
• FLWARL
Bit Bit Name Initial Value Slave Host Description
7 FWA14 1
6 FWA13 1
5 FWA12 1
4 FWA11 0
3 FWA10 1
2 FWA9 1
1 FWA8 1
0 FWA7 1
Note: Can be written to by the FLWAR set command.
*
R/W

R Reserved
These bits are read as 0 and cannot be modified.
R W* Flash Memory Programming Start Address 19 to 15
R W*
R W*
R W*
R W*
R/W
R W* Flash Memory Programming Start Addresses 14 to 7
R W*
R W*
R W*
R W*
R W*
R W*
R W*
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 655 of 986
REJ09B0098-0300