10.8.10 Conflict Between Overflow/Underflow And Counter Clearing; 10.8.11 Conflict Between Tcnt Write And Overflow/Underflow - Renesas H8S/2100 Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)

10.8.10 Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a
TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Figure 10.51 Conflict between Overflow and Counter Clearing

10.8.11 Conflict between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set. Figure 10.52 shows the operation timing when there is conflict between TCNT write and
overflow.
φ
Address
Write signal
TCNT
TCFV flag
Figure 10.52 Conflict between TCNT Write and Overflow
Rev. 1.00 May 09, 2008 Page 288 of 954
REJ09B0462-0100
φ
TCNT input
clock
TCNT H'FFFF
Counter
clear signal
TGF
Disabled
TCFV
H'FFFF
H'0000
state of a TCNT write cycle, and
2
TCNT write cycle
T1 T2
TCNT address
M
TCNT write data