Renesas H8S Series Hardware Manual page 25

18.3.14 RAM Buffer Address Register (RBUFAR) .......................................................... 654
18.3.15 Flash Memory Programming Address Registers H and L
(FLWARH and FLARL)....................................................................................... 655
18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register
(LMCDIDCR)....................................................................................................... 656
18.3.17 Erase Block Register (EBLKR) ............................................................................ 657
18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2)..................................... 658
18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2) ................................. 662
18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L).................... 665
18.3.21 Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L).................... 666
18.3.22 On-Chip RAM Host Base Address Registers H and L
(RAMBARH and RAMBARL) ............................................................................ 667
18.3.23 Address Space Set Register (ASSR)..................................................................... 668
18.3.24 On-Chip RAM Address Space Set Register (RAMASSR) ................................... 669
18.3.25 Slave Address Register 1 (SAR1)......................................................................... 670
18.3.26 Slave Address Register 2 (SAR2)......................................................................... 671
18.3.27 On-Chip RAM Slave Address Register (RAMAR) .............................................. 671
18.3.28 Flash Memory Write Protect Registers H, M, and L
(FWPRH, FWPRM, and FWPRL)........................................................................ 672
18.3.29 Flash Memory Read Protect Registers H, M, and L
(FRPRH, FRPRM, and FRPRL) ........................................................................... 674
18.3.30 On-Chip RAM Protect Control Register (MPCR) ................................................ 676
18.3.31 User Command Register (UCMDTR) .................................................................. 676
18.4 Operation ........................................................................................................................... 677
18.4.1 LPC interface Activation ...................................................................................... 677
18.4.2 LPC I/O Cycles..................................................................................................... 677
18.4.3 Gate A20............................................................................................................... 680
18.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 683
18.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 687
18.4.6 LPC Interface Clock Start Request ....................................................................... 689
18.4.7 LPC/FW Memory Cycle ....................................................................................... 689
18.4.8 LPC/FW Memory Access Command ................................................................... 692
18.4.9 Flash Memory Address Translation (Host → Slave) ............................................ 700
18.4.10 On-Chip RAM Address Translation (Host → Slave) ........................................... 701
18.4.11 Address Space Priority.......................................................................................... 702
18.4.12 Example 1 of Address Space Priority ................................................................... 703
18.4.13 Example 2 of Address Space Priority ................................................................... 704
18.4.14 Flash Memory Protection...................................................................................... 705
18.4.15 On-Chip RAM Protection ..................................................................................... 707
18.4.16 Flash Memory Programming ................................................................................ 707
Rev. 3.00 Jul. 14, 2005 Page xxv of xlviii