Interrupt Exception Handling Sequence - Renesas H8S Series Hardware Manual
16-bit single-chip microcomputer
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Section 5 Interrupt Controller
5.6.3
Interrupt Exception Handling Sequence
Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev. 3.00 Jul. 14, 2005 Page 117 of 986
REJ09B0098-0300
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