Dtc Vector Register (Dtvecr) - Renesas H8S Series Hardware Manual

Section 7 Data Transfer Controller (DTC)
7.2.8

DTC Vector Register (DTVECR)

DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit Bit Name Initial Value
7 SWDTE 0
6 DTVEC6 0
5 DTVEC5 0
4 DTVEC4 0
3 DTVEC3 0
2 DTVEC2 0
1 DTVEC1 0
0 DTVEC0 0
Rev. 3.00 Jul. 14, 2005 Page 142 of 986
REJ09B0098-0300
R/W Description
R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can always
be written to this bit. Writing 0 is enabled only after 1
has been read.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified number
of transfers have not ended
•
When 0 is written to the DISEL bit after a software-
activated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
[Holding conditions]
•
When the DISEL bit is set to 1 and data transfer
has ended
•
The specified number of transfers have ended
•
On data transfer by software activation
R/W DTC Software Activation Vectors 6 to 0
R/W These bits specify a vector number for DTC software
activation.
R/W
The vector address is expressed as H'0400 + (vector
R/W
number × 2). For example, when DTVEC6 to DTVEC0
R/W
= H'10, the vector address is H'0420. When the
SWDTE bit is 0, these bits can be written to.
R/W
R/W