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Renesas H8S series Manuals
Manuals and User Guides for Renesas H8S series. We have
9
Renesas H8S series manuals available for free PDF download: Hardware Manual, User Manual
Renesas H8S series Hardware Manual (1038 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.77 MB
Table of Contents
General Precautions on Handling of Product
4
Preface
6
Table of Contents
11
Section 1 Overview
49
Overview
49
Section 1 Overview
50
Internal Block Diagram
51
Figure 1.1 H8S/2114R Group Internal Block Diagram
51
Pin Description
52
Pin Arrangement
52
Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)
52
Pin Arrangement in each Operating Mode
53
Table 1.1 H8S/2114R Group Pin Arrangement in each Operating Mode
53
Overview
53
Pin Functions
58
Table 1.2 Pin Functions
58
Electrical Characteristics
59
Figure 1.3 Sample Design of Reset Signals with no Affection each Other
65
Section 2 CPU
67
Features
67
Differences between H8S/2600 CPU and H8S/2000 CPU
68
Differences from H8/300 CPU
69
Differences from H8/300H CPU
69
CPU Operating Modes
70
Normal Mode
70
Figure 2.1 Exception Vector Table (Normal Mode)
71
Figure 2.2 Stack Structure in Normal Mode
71
Advanced Mode
72
Figure 2.3 Exception Vector Table (Advanced Mode)
72
Figure 2.4 Stack Structure in Advanced Mode
73
Address Space
74
Figure 2.5 Memory Map
74
Register Configuration
75
Figure 2.6 CPU Internal Registers
75
Figure 2.7 Usage of General Registers
76
General Registers
76
Extended Control Register (EXR)
77
Figure 2.8 Stack
77
Program Counter (PC)
77
Condition-Code Register (CCR)
78
Initial Register Values
79
Data Formats
80
General Register Data Formats
80
Figure 2.9 General Register Data Formats (1)
80
Figure 2.9 General Register Data Formats (2)
81
Memory Data Formats
82
Figure 2.10 Memory Data Formats
82
Instruction Set
83
Table 2.1 Instruction Classification
83
Table 2.2 Operation Notation
84
Table of Instructions Classified by Function
84
Table 2.3 Data Transfer Instructions
85
Table 2.4 Arithmetic Operations Instructions (1)
86
Table 2.4 Arithmetic Operations Instructions (2)
87
Table 2.5 Logic Operations Instructions
88
Table 2.6 Shift Instructions
89
Table 2.7 Bit Manipulation Instructions (1)
90
Table 2.7 Bit Manipulation Instructions (2)
91
Table 2.8 Branch Instructions
92
Table 2.9 System Control Instructions
93
Table 2.10 Block Data Transfer Instructions
94
Basic Instruction Formats
95
Figure 2.11 Instruction Formats (Examples)
95
Addressing Modes and Effective Address Calculation
96
Register Direct-Rn
96
Register Indirect-@Ern
96
Table 2.11 Addressing Modes
96
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
97
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
97
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
97
Immediate-#XX:8, #XX:16, or #XX:32
98
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
98
Table 2.12 Absolute Address Access Ranges
98
Memory Indirect-@@Aa:8
99
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
99
Effective Address Calculation
100
Table 2.13 Effective Address Calculation (1)
100
Table 2.13 Effective Address Calculation (2)
101
Processing States
102
Figure 2.13 State Transitions
103
Usage Notes
104
Note on TAS Instruction Usage
104
Note on STM/LDM Instruction Usage
104
Note on Bit Manipulation Instructions
104
EEPMOV Instruction
105
Section 3 MCU Operating Modes
107
Operating Mode Selection
107
Register Descriptions
108
Mode Control Register (MDCR)
108
System Control Register (SYSCR)
109
Serial Timer Control Register (STCR)
111
System Control Register 3 (SYSCR3)
114
Operating Mode Descriptions
115
Mode 2
115
Mode 3
115
Address Map
115
Figure 3.1 Address Map
116
Section 4 Exception Handling
117
Exception Handling Types and Priority
117
Table 4.1 Exception Types and Priority
117
Exception Sources and Exception Vector Table
118
Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode)
118
Table 4.3 Exception Handling Vector Table (Extended Vector Mode)
120
Reset
122
Reset Exception Handling
122
Interrupts Immediately after Reset
123
On-Chip Peripheral Modules after Reset Is Cancelled
123
Figure 4.1 Reset Sequence (Mode 2)
123
Interrupt Exception Handling
124
Trap Instruction Exception Handling
124
Table 4.4 Status of CCR after Trap Instruction Exception Handling
124
Stack Status after Exception Handling
125
Figure 4.2 Stack Status after Exception Handling
125
Usage Note
126
Figure 4.3 Operation When SP Value Is Odd
126
Section 5 Interrupt Controller
127
Features
127
Figure 5.1 Block Diagram of Interrupt Controller
128
Input/Output Pins
129
Table 5.1 Pin Configuration
129
Register Descriptions
130
Interrupt Control Registers a to D (ICRA to ICRD)
131
Table 5.2 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0)
131
Table 5.3 Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1)
132
Address Break Control Register (ABRKCR)
133
Break Address Registers a to C (BARA to BARC)
134
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
135
IRQ Enable Registers (IER16, IER)
138
IRQ Status Registers (ISR16, ISR)
139
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB)
141
Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts
143
Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (Extended Vector Mode: EIVS = 1)
144
IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
145
Interrupt Sources
147
External Interrupt Sources
147
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0
148
Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8)
149
Internal Interrupt Sources
150
Interrupt Exception Handling Vector Tables
150
Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode)
151
Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode)
154
Interrupt Control Modes and Interrupt Operation
157
Table 5.6 Interrupt Control Modes
157
Figure 5.6 Block Diagram of Interrupt Control Operation
158
Table 5.7 Interrupts Selected in each Interrupt Control Mode
159
Interrupt Control Mode 0
160
Table 5.8 Operations and Control Signal Functions in each Interrupt Control Mode
160
Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
161
Figure 5.8 State Transition in Interrupt Control Mode 1
162
Interrupt Control Mode 1
162
Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1
164
Interrupt Exception Handling Sequence
165
Figure 5.10 Interrupt Exception Handling
166
Interrupt Response Times
167
Table 5.9 Interrupt Response Times
167
DTC Activation by Interrupt
168
Figure 5.11 Interrupt Control for DTC
168
Table 5.10 Interrupt Source Selection and Clearing Control
169
Address Breaks
170
Features
170
Block Diagram
170
Figure 5.12 Block Diagram of Address Break Function
170
Operation
171
Usage Notes
171
Figure 5.13 Examples of Address Break Timing
172
Usage Notes
173
Conflict between Interrupt Generation and Disabling
173
Figure 5.14 Conflict between Interrupt Generation and Disabling
173
Instructions for Disabling Interrupts
174
Interrupts During Execution of EEPMOV Instruction
174
Vector Address Switching
174
External Interrupt Pin in Software Standby Mode and Watch Mode
175
Noise Canceller Switching
175
IRQ Status Register (ISR)
175
Section 6 Bus Controller (BSC)
177
Features
177
Figure 6.1 Block Diagram of BSC
177
Register Descriptions
178
Bus Control Register (BCR)
178
Wait State Control Register (WSCR)
179
Bus Arbitration
180
Priority of Bus Masters
180
Bus Transfer Timing
180
Section 7 Data Transfer Controller (DTC)
183
Features
184
Figure 7.1 Block Diagram of DTC
184
Register Descriptions
185
DTC Mode Register a (MRA)
186
DTC Mode Register B (MRB)
187
DTC Source Address Register (SAR)
187
DTC Destination Address Register (DAR)
188
DTC Transfer Count Register a (CRA)
188
DTC Transfer Count Register B (CRB)
188
DTC Enable Registers (DTCER)
189
Table 7.1 Correspondence between Interrupt Sources and DTCER
189
DTC Vector Register (DTVECR)
190
Activation Sources
191
Figure 7.2 Block Diagram of DTC Activation Source Control
191
Location of Register Information and DTC Vector Table
192
Figure 7.3 DTC Register Information Location in Address Space
192
Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
193
Operation
195
Figure 7.4 DTC Operation Flowchart
195
Figure 7.5 Memory Mapping in Normal Mode
196
Normal Mode
196
Table 7.3 Register Functions in Normal Mode
196
Figure 7.6 Memory Mapping in Repeat Mode
197
Repeat Mode
197
Table 7.4 Register Functions in Repeat Mode
197
Block Transfer Mode
198
Figure 7.7 Memory Mapping in Block Transfer Mode
198
Table 7.5 Register Functions in Block Transfer Mode
198
Chain Transfer
199
Figure 7.8 Chain Transfer Operation
199
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
200
Interrupt Sources
200
Operation Timing
200
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
201
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
201
Number of DTC Execution States
202
Table 7.6 DTC Execution Status
202
Table 7.7 Number of States Required for each Execution Status
202
Procedures for Using DTC
203
Activation by Interrupt
203
Activation by Software
203
Examples of Use of the DTC
204
Normal Mode
204
Software Activation
205
Usage Notes
206
Module Stop Mode Setting
206
On-Chip RAM
206
DTCE Bit Setting
206
Setting Required on Entering Subactive Mode or Watch Mode
206
DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter
206
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Renesas H8S series Hardware Manual (875 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.48 MB
Table of Contents
General Precautions on Handling of Product
5
Preface
7
List of Registers
8
Register Bits
16
Table of Contents
21
Section 1 Overview
53
Features
53
Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363
55
Block Diagram
55
Figure
55
Figure 1.2 Internal Block Diagram of H8S/2366
56
Pin Description
57
Pin Arrangement
57
Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363
57
Figure 1.4 Pin Arrangement of H8S/2366
58
Figure 1.5 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363
59
Figure 1.6 Pin Arrangement of H8S/2366
60
Pin Arrangement in each Operating Mode
61
Table 1.1 Pin Arrangement in each Operating Mode
61
Manual
62
Pin Functions
66
Table 1.2 Pin Functions
66
Section 2 CPU
73
Features
73
Differences between H8S/2600 CPU and H8S/2000 CPU
74
Differences from H8/300 CPU
75
Differences from H8/300H CPU
75
CPU Operating Modes
76
Normal Mode
76
Advanced Mode
77
Figure 2.1 Exception Vector Table (Normal Mode)
77
Figure 2.2 Stack Structure in Normal Mode
77
Figure 2.3 Exception Vector Table (Advanced Mode)
78
Figure 2.4 Stack Structure in Advanced Mode
79
Figure 2.5 Memory Map
80
Address Space
80
Figure 2.6 CPU Internal Registers
81
Figure 2.7 Usage of General Registers
82
General Registers
82
Extended Control Register (EXR)
83
Program Counter (PC)
83
Stack
83
Condition-Code Register (CCR)
84
Initial Register Values
86
Register Configuration
81
Data Formats
86
Figure 2.9 General Register Data Formats (1)
86
General Register Data Formats
86
Figure 2.9 General Register Data Formats (2)
87
Figure 2.10 Memory Data Formats
88
Memory Data Formats
88
Table 2.1
89
Table 2.2 Operation Notation
90
Table of Instructions Classified by Function
90
Table 2.3 Data Transfer Instructions
91
Table 2.4 Arithmetic Operations Instructions
92
Table 2.5 Logic Operations Instructions
94
Table 2.6 Shift Instructions
94
Table 2.7 Bit Manipulation Instructions
95
Table 2.8 Branch Instructions
97
Table 2.9 System Control Instructions
98
Basic Instruction Formats
99
Table 2.10 Block Data Transfer Instructions
99
Instruction Set
89
Table 2.11 Addressing Modes
100
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
101
Register Direct-Rn
101
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
101
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
101
Register Indirect-@Ern
101
Immediate-#XX:8, #XX:16, or #XX:32
102
Memory Indirect-@@Aa:8
102
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
102
Table 2.12 Absolute Address Access Ranges
102
Effective Address Calculation
103
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
103
Table 2.13 Effective Address Calculation
104
Figure 2.11 Instruction Formats (Examples)
100
Addressing Modes and Effective Address Calculation
100
Processing States
106
Usage Note
107
Note on Bit Manipulation Instructions
107
Figure 2.13 State Transitions
107
Section 3 MCU Operating Modes
109
Operating Mode Selection
109
Register Descriptions
110
Mode Control Register (MDCR)
110
System Control Register (SYSCR)
110
Operating Mode Descriptions
112
Mode 1
112
Mode 2
112
Mode 3
112
Mode 4
112
Mode 7
113
Pin Functions
113
Table 3.2 Pin Functions in each Operating Mode
113
Memory Map in each Operating Mode
114
Figure 3.1 H8S/2367 Memory Map (1)
114
Figure 3.2 H8S/2367 Memory Map (2)
115
Figure 3.3 H8S/2366 Memory Map (1)
116
Figure 3.4 H8S/2366 Memory Map (2)
117
Figure 3.5 H8S/2365 Memory Map (1)
118
Figure 3.6 H8S/2365 Memory Map (2)
119
Figure 3.7 H8S/2363 Memory Map
120
Section 4 Exception Handling
121
Table 4.1 Exception Types and Priority
121
Exception Handling Types and Priority
121
Exception Sources and Exception Vector Table
121
Table 4.2 Exception Handling Vector Table
122
Reset
123
Reset Exception Handling
123
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)
124
Interrupts after Reset
125
On-Chip Peripheral Functions after Reset Release
125
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)
125
Table 4.3 Status of CCR and EXR after Trace Exception Handling
126
Traces
126
Interrupts
126
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
127
Trap Instruction
127
Stack Status after Exception Handling
128
Figure 4.3 Stack Status after Exception Handling
128
Usage Notes
129
Figure 4.4 Operation When SP Value Is Odd
129
Section 5 Interrupt Controller
131
Features
131
Figure 5.1 Block Diagram of Interrupt Controller
132
Table 5.1 Pin Configuration
133
Interrupt Control Register (INTCR)
134
Interrupt Priority Registers a to K (IPRA to IPRK)
134
IRQ Enable Register (IER)
136
IRQ Sense Control Register L (ISCRL)
137
IRQ Status Register (ISR)
140
IRQ Pin Select Register (ITSR)
141
Software Standby Release IRQ Enable Register (SSIER)
142
Input/Output Pins
133
Register Descriptions
133
Interrupt Sources
142
External Interrupts
142
Internal Interrupts
143
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
143
Interrupt Exception Handling Vector Table
144
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
145
Interrupt Control Modes and Interrupt Operation
149
Interrupt Control Mode 0
149
Table 5.3 Interrupt Control Modes
149
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance
150
Interrupt Control Mode 2
151
Interrupt Exception Handling Sequence
152
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 2
152
Figure 5.5 Interrupt Exception Handling
153
Interrupt Response Times
154
Table 5.4 Interrupt Response Times
154
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses
154
DTC and DMAC* Activation by Interrupt
155
Usage Notes
155
Contention between Interrupt Generation and Disabling
155
Instructions that Disable Interrupts
156
Times When Interrupts Are Disabled
156
Interrupts During Execution of EEPMOV Instruction
156
Figure 5.6 Contention between Interrupt Generation and Disabling
156
Change of IRQ Pin Select Register (ITSR) Setting
157
Note on IRQ Status Register (ISR)
157
Section 6 Bus Controller (BSC)
159
Features
159
Figure 6.1 Block Diagram of Bus Controller
160
Input/Output Pins
161
Table 6.1 Pin Configuration
161
Register Descriptions
162
Bus Width Control Register (ABWCR)
163
Access State Control Register (ASTCR)
163
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL)
164
Read Strobe Timing Control Register (RDNCR)
169
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
169
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
170
Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and Rdnn = 0)
171
Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL)
172
Bus Control Register (BCR)
173
DRAM Control Register (DRAMCR)
175
Figure 6.4 RAS Signal Assertion Timing
179
DRAM Access Control Register (DRACCR)
180
Refresh Control Register (REFCR)
181
Refresh Timer Counter (RTCNT)
184
Refresh Time Constant Register (RTCOR)
184
Operation
184
Area Division
184
Figure 6.5 Area Divisions
185
Bus Specifications
186
Table 6.2 Bus Specifications for each Area (Basic Bus Interface)
187
Memory Interfaces
188
Chip Select Signals
189
Figure 6.6 Csn Signal Output Timing (N = 0 to 7)
189
Basic Bus Interface
190
Data Size and Data Alignment
190
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space)
190
Valid Strobes
191
Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Space)
191
Table 6.3 Data Buses Used and Valid Strobes
191
Basic Timing
192
Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space
192
Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space
193
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)
194
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)
195
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
196
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)
197
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)
198
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
199
Wait Control
200
Read Strobe (RD) Timing
201
Figure 6.17 Example of Wait State Insertion Timing
201
Extension of Chip Select (CS) Assertion Period
202
Figure 6.18 Example of Read Strobe Timing
202
Figure 6.19 Example of Timing When Chip Select Assertion Period Is Extended
203
Renesas H8S series Hardware Manual (1047 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.54 MB
Table of Contents
Table of Contents
13
Section 1 Overview
29
Overview
29
Block Diagram
34
Pin Description
35
Pin Arrangement
35
Pin Functions in each Operating Mode
39
Pin Functions
43
Section 2 CPU
49
Overview
49
Features
49
Differences between H8S/2600 CPU and H8S/2000 CPU
50
Differences from H8/300 CPU
50
Differences from H8/300H CPU
51
CPU Operating Modes
51
Advanced Mode
51
Address Space
54
Register Configuration
55
Overview
55
General Registers
55
Control Registers
56
Initial Register Values
57
Data Formats
58
General Register Data Formats
58
Memory Data Formats
60
Instruction Set
61
Overview
61
Instructions and Addressing Modes
62
Table of Instructions Classified by Function
63
Basic Instruction Formats
69
Addressing Modes and Effective Address Calculation
69
Addressing Mode
69
Effective Address Calculation
72
Processing States
75
Overview
75
Reset State
76
Exception-Handling State
76
Program Execution State
78
Bus-Released State
78
Power-Down State
78
Basic Timing
79
Overview
79
On-Chip Memory (ROM, RAM)
79
On-Chip Supporting Module Access Timing
80
External Address Space Access Timing
81
Usage Note
81
TAS Instruction
81
Section 3 MCU Operating Modes
83
Overview
83
Operating Mode Selection (H8S/2357 F-ZTAT Only)
83
Operating Mode Selection (ZTAT, Masked ROM, Romless Version, and H8S/2398 F-ZTAT)
84
Register Configuration
85
Register Descriptions
85
Mode Control Register (MDCR)
85
System Control Register (SYSCR)
85
System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
86
Operating Mode Descriptions
88
Mode 1
88
Mode 2 (H8S/2398 F-ZTAT Only)
88
Mode 3 (H8S/2398 F-ZTAT Only)
88
Mode 4 (On-Chip ROM Disabled Expansion Mode)
88
Mode 5 (On-Chip ROM Disabled Expansion Mode)
88
Mode 6 (On-Chip ROM Enabled Expansion Mode)
88
Mode 7 (Single-Chip Mode)
89
Modes 8 and 9
89
Mode 10 (H8S/2357 F-ZTAT Only)
89
Mode 11 (H8S/2357 F-ZTAT Only)
89
Modes 12 and 13 (H8S/2357 F-ZTAT Only)
89
Mode 14 (H8S/2357 F-ZTAT Only)
89
Mode 15 (H8S/2357 F-ZTAT Only)
89
Pin Functions in each Operating Mode
90
Memory Map in each Operating Mode
90
Section 4 Exception Handling
99
Overview
99
Exception Handling Types and Priority
99
Exception Handling Operation
100
Exception Vector Table
100
Reset
102
Overview
102
Reset Types
102
Reset Sequence
103
Interrupts after Reset
104
State of On-Chip Supporting Modules after Reset Release
104
Traces
104
Interrupts
105
Trap Instruction
106
Stack Status after Exception Handling
106
Notes on Use of the Stack
107
Section 5 Interrupt Controller
109
Overview
109
Features
109
Block Diagram
110
Pin Configuration
110
Register Configuration
111
Register Descriptions
111
System Control Register (SYSCR)
111
Interrupt Priority Registers a to K (IPRA to IPRK)
112
IRQ Enable Register (IER)
113
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
114
IRQ Status Register (ISR)
114
Interrupt Sources
115
External Interrupts
115
Internal Interrupts
116
Interrupt Exception Handling Vector Table
116
Interrupt Operation
119
Interrupt Control Modes and Interrupt Operation
119
Interrupt Control Mode 0
121
Interrupt Control Mode 2
123
Interrupt Exception Handling Sequence
125
Interrupt Response Times
126
Usage Notes
127
Contention between Interrupt Generation and Disabling
127
Instructions that Disable Interrupts
127
Times When Interrupts Are Disabled
128
Interrupts During Execution of EEPMOV Instruction
128
DTC and DMAC Activation by Interrupt
128
Overview
128
Block Diagram
129
Operation
129
Note on Use
130
Section 6 Bus Controller
131
Overview
131
Features
131
Block Diagram
133
Pin Configuration
134
Register Configuration
135
Register Descriptions
136
Bus Width Control Register (ABWCR)
136
Access State Control Register (ASTCR)
137
Wait Control Registers H and L (WCRH, WCRL)
138
Bus Control Register H (BCRH)
141
Bus Control Register L (BCRL)
142
Memory Control Register (MCR)
144
DRAM Control Register (DRAMCR)
146
Refresh Timer/Counter (RTCNT)
147
Refresh Time Constant Register (RTCOR)
148
Overview of Bus Control
149
Area Partitioning
149
Bus Specifications
150
Memory Interfaces
151
Advanced Mode
151
Chip Select Signals
152
Basic Bus Interface
153
Overview
153
Data Size and Data Alignment
153
Valid Strobes
155
Basic Timing
156
Wait Control
164
DRAM Interface
166
Overview
166
Setting DRAM Space
166
Address Multiplexing
166
Data Bus
166
Pins Used for DRAM Interface
167
Basic Timing
168
Precharge State Control
169
Wait Control
169
Byte Access Control
171
Burst Operation
172
Refresh Control
175
DMAC Single Address Mode and DRAM Interface
177
When DDS = 1
177
When DDS = 0
178
Burst ROM Interface
178
Overview
178
Basic Timing
179
Wait Control
180
Idle Cycle
181
Operation
181
Usage Notes
183
Pin States in Idle Cycle
185
Write Data Buffer Function
186
Bus Release
187
Overview
187
Operation
187
Pin States in External Bus Released State
188
Transition Timing
189
Usage Note
189
Bus Arbitration
190
Overview
190
Operation
190
Bus Transfer Timing
191
External Bus Release Usage Note
191
Resets and the Bus Controller
192
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Renesas H8S series Hardware Manual (609 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 3.18 MB
Table of Contents
Table of Contents
11
Section 1 Overview
37
Overview
37
Internal Block Diagram
39
Figure 1.1 Internal Block Diagram (HD64F2612, HD6432612, and HD6432611)
39
Section 1 Overview
39
Figure 1.2 Internal Block Diagram (HD6432616 and HD6432614)
40
Pin Arrangement
41
Figure 1.3 Pin Arrangement (HD64F2612, HD6432612, and HD6432611)
41
Figure 1.4 Pin Arrangement (HD6432616 and HD6432614)
42
Pin Functions
43
Differences between H8S/2612, H8S/2611, H8S/2614, and H8S/2616
48
Table 1.1 Comparison of Product Specifications
48
Section 2 CPU
49
Features
49
Differences between H8S/2600 CPU and H8S/2000 CPU
50
Section 2 CPU
50
Differences from H8/300 CPU
51
Differences from H8/300H CPU
51
CPU Operating Modes
52
Normal Mode
52
Advanced Mode
53
Figure 2.1 Exception Vector Table (Normal Mode)
53
Figure 2.2 Stack Structure in Normal Mode
53
Figure 2.3 Exception Vector Table (Advanced Mode)
54
Figure 2.4 Stack Structure in Advanced Mode
55
Address Space
56
Figure 2.5 Memory Map
56
Register Configuration
57
Figure 2.6 CPU Registers
57
Figure 2.7 Usage of General Registers
58
General Registers
58
Extended Control Register (EXR)
59
Figure 2.8 Stack
59
Program Counter (PC)
59
Condition-Code Register (CCR)
60
Initial Values of CPU Registers
62
Multiply-Accumulate Register (MAC)
62
Data Formats
63
General Register Data Formats
63
Figure 2.9 General Register Data Formats (1)
63
Figure 2.9 General Register Data Formats (2)
64
Memory Data Formats
65
Figure 2.10 Memory Data Formats
65
Instruction Set
66
Table 2.1 Instruction Classification
66
Table 2.2 Operation Notation
67
Table of Instructions Classified by Function
67
Table 2.3 Data Transfer Instructions
68
Table 2.4 Arithmetic Operations Instructions
69
Table 2.5 Logic Operations Instructions
71
Table 2.6 Shift Instructions
71
Table 2.7 Bit Manipulation Instructions
72
Table 2.8 Branch Instructions
74
Table 2.9 System Control Instructions
75
Basic Instruction Formats
76
Table 2.10 Block Data Transfer Instructions
76
Figure 2.11 Instruction Formats (Examples)
77
Addressing Modes and Effective Address Calculation
78
Register Direct-Rn
78
Register Indirect-@Ern
78
Table 2.11 Addressing Modes
78
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
79
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
79
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
79
Immediate-#XX:8, #XX:16, or #XX:32
80
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
80
Memory Indirect-@@Aa:8
80
Table 2.12 Absolute Address Access Ranges
80
Effective Address Calculation
81
Figure 2.12 Branch Address Specification in Memory Indirect Mode
81
Processing States
84
Usage Notes
85
Usage Notes on Bit Manipulation Instructions
85
Figure 2.13 State Transitions
85
Section 3 MCU Operating Modes
87
Operating Mode Selection
87
Register Descriptions
87
Table 3.1 MCU Operating Mode Selection
87
Mode Control Register(MDCR)
88
System Control Register(SYSCR)
89
Pin Functions in each Operating Mode
90
Pin Functions
90
Table 3.2 Pin Functions in each Mode
90
Address Map
91
Figure 3.1 Address Map (H8S/2612, H8S/2611, H8S/2616, H8S/2614)
91
Section 4 Exception Handling
93
Exception Handling Types and Priority
93
Exception Sources and Exception Vector Table
93
Table 4.1 Exception Types and Priority
93
Table 4.2 Exception Handling Vector Table
94
Reset
95
Reset Exception Handling
95
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)
96
Interrupts after Reset
97
State of On-Chip Supporting Modules after Reset Release
97
Figure 4.2 Reset Sequence
97
Traces
98
Interrupts
98
Table 4.3 Status of CCR and EXR after Trace Exception Handling
98
Trap Instruction
99
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
99
Stack Status after Exception Handling
100
Figure 4.3 Stack Status after Exception Handling
100
Usage Note
101
Figure 4.4 Operation When SP Value Is Odd
101
Section 5 Interrupt Controller
103
Features
103
Figure 5.1 Block Diagram of Interrupt Controller
104
Input/Output Pins
105
Register Descriptions
105
Interrupt Priority Registers a to H, J, K, M (IPRA to IPRH,IPRJ, IPRK, IPRM)
106
IRQ Enable Register (IER)
107
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
107
IRQ Status Register (ISR)
110
Interrupt
111
External Interrupts
111
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
111
Internal Interrupts
112
Interrupt Exception Handling Vector Table
112
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
113
Interrupt Control Modes and Interrupt Operation
115
Interrupt Control Mode 0
115
Table 5.3 Interrupt Control Modes
115
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control
116
Interrupt Control Mode 2
117
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Control Mode 2
118
Interrupt Exception Handling Sequence
119
Figure 5.5 Interrupt Exception Handling
120
Interrupt Response Times
121
Table 5.4 Interrupt Response Times
121
DTC Activation by Interrupt
122
Usage Notes
122
Contention between Interrupt Generation and Disabling
122
Table 5.5 Number of States in Interrupt Handling Routine Execution Status
122
Instructions that Disable Interrupts
123
When Interrupts Are Disabled
123
Figure 5.6 Contention between Interrupt Generation and Disabling
123
Interrupts During Execution of EEPMOV Instruction
124
Section 6 PC Break Controller (PBC)
125
Features
125
Register Descriptions
126
Break Address Register a (BARA)
126
Figure 6.1 Block Diagram of PC Break Controller
126
Break Address Register B (BARB)
127
Break Control Register a (BCRA)
127
Break Control Register B (BCRB)
128
Operation
128
PC Break Interrupt Due to Instruction Fetch
128
PC Break Interrupt Due to Data Access
128
Notes on PC Break Interrupt Handling
129
Operation in Transitions to Power-Down Modes
129
Figure 6.2 Operation in Power-Down Mode Transitions
129
When Instruction Execution Is Delayed by One State
130
Usage Notes
131
Module Stop Mode Setting
131
PC Break Interrupts
131
CMFA and CMFB
131
PC Break Interrupt When DTC Is Bus Master
131
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction
131
I Bit Set by LDC, ANDC, ORC, or XORC Instruction
131
PC Break Set for Instruction Fetch at Address Following Bcc Instruction
132
PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction
132
Renesas H8S series User Manual (26 pages)
Direct Drive LCD
Brand:
Renesas
| Category:
Computer Hardware
| Size: 0.77 MB
Table of Contents
Table of Contents
2
1 Introduction
4
Direct Drive Lcd Overview
4
Philosophy
4
Capabilities
4
2 Driver Configuration
5
Lcd Direct Drive Configuration Macros
5
2.2 Frame Buffer Configuration
7
Frame_Height
7
Frame_Width
7
V_Lines_Invert
7
H_Dot_Invert
7
Panel_Rotate
7
Lcd_Frames
7
Max_Frame_Regions
7
Driver Mode Selection
9
Sram_Dd
9
Sram_Nomux_Dd
9
Sdram_Dd
9
Sdram_Cluster_Dd
9
Dot Clock Hardware Connections
9
Driver Mode Configuration
10
Dot_Clock_Frequency_Data
10
Dot_Clock_Frequency_Blank
10
Desired_Frame_Rate
10
Minimum_Mcu_Access_Pct
10
Lcd Panel Configuration
10
Dot_Invert
10
V_Lines_Xx and H_Dot_Xx
10
2.6 LCD Platform Configuration
11
Frame_Cs
11
Frame_Bus_Cycles
11
Cas_Latency
11
Sdram_Page_Size
11
Edmac_Dd
11
Xxxx_Port
11
Xxxx_Pin
11
Xxxx_Intc
11
Xxxx_Vect
11
Xxxx_Tpu_Channel
12
Xxxx_Tpu_Pin
12
3 Typical Lcd Panel Connections
13
Lcd Panel Interface
13
Power Supplies
13
Clock
13
Hsync
13
Vsync
13
Data Enable
14
RGB (Red Green Blue) Data
14
Touch Screen
14
3.2 Hardware Design
15
Renesas H8S series User Manual (38 pages)
Brand:
Renesas
| Category:
Computer Hardware
| Size: 0.95 MB
Table of Contents
Table of Contents
4
Connecting the Emulator with the User System
5
Components of the E10A-USB Emulator
5
Connecting the E10A-USB Emulator with the User System
7
Pin Assignments of the E10A-USB Connector
9
Example of Emulator Connection
10
Specification of the Emulator's Software
13
Differences between the H8SX/1725F, H8SX/1725SF, H8SX/1727SF, and the Emulator
13
The H8SX/1725F, H8SX/1725SF, or H8SX/1727SF E10A-USB Emulator Specific Functions and Notes
17
Emulator Driver Selection
17
Hardware Break Functions
18
Notes on Setting the [Breakpoint] Dialog Box
20
Sequential Break Function
21
Note on Using the JTAG Clock (TCK)
21
Trace Function
21
Parallel Transfer
22
Debugging in the External Flash Memory
24
Interface with Initialization, Write, and Erase Modules and Emulator Firmware
28
Performance Analysis
30
Renesas H8S series User Manual (32 pages)
User System Interface Cable for E6000 Emulator
Brand:
Renesas
| Category:
Cables and connectors
| Size: 0.51 MB
Table of Contents
Table of Contents
15
Section 1 Configuration
16
Section 2 Connection Procedures
18
Connecting User System Interface Cable to Emulator Station
18
Connecting User System Interface Cable to User System
20
Installing IC Socket
20
Soldering IC Socket
20
Inserting Cable Head
21
Fastening Cable Head
21
Fastening Cable Body
23
Recommended Dimensions for User System Mount Pad
24
Dimensions for User System Interface Cable Head
25
Resulting Dimensions after Connecting User System Interface Cable
26
Section 3 Installing the MCU to the User System
27
Section 4 Verifying Operation
29
Section 5 Setting P81, P83, and P85 Jumper Sockets
30
Section 6 Notice
31
Renesas H8S series User Manual (31 pages)
E10A-USB Emulator
Brand:
Renesas
| Category:
Media Converter
| Size: 0.32 MB
Table of Contents
Table of Contents
5
Connecting the Emulator with the User System
7
Components of the E10A-USB Emulator
7
Connecting the E10A-USB Emulator with the User System
9
Pin Assignments of the E10A-USB Connector
10
Example of Emulator Connection
11
Specifications of the Emulator's Software
15
Differences between the H8S/2427, H8S/2427R, H8S/2425 Group and the Emulator
15
The H8S/2427 E10A-USB and H8S/2425 E10A-USB Emulator Functions
18
Emulator Driver Selection
18
Hardware Break Functions
18
Notes on Setting the [Breakpoint] Dialog Box
20
Note on Using the JTAG Clock (TCK)
20
Trace Function
21
Debugging in the External Flash Memory
21
Interface with Initialization, Write, and Erase Modules and Emulator Firmware
25
Renesas H8S series User Manual (21 pages)
LCD Display Using 1/4 Duty Drive (LCD Controller/Driver)
Brand:
Renesas
| Category:
Computer Hardware
| Size: 0.13 MB
Table of Contents
Table of Contents
3
Specifications
4
Functions Used
5
Principles of Operation
12
Description of Software
14
Flowchart
17
Program Listings
18
Link Addresses
19
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