Subsleep Mode - Renesas H8S Series Hardware Manual

Section 24 Power-Down Modes
24.8

Subsleep Mode

The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in
subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1,
and the PSS bit in TCSR (WDT_1) set to 1.
In subsleep mode, the CPU is stopped. On-chip peripheral modules other than TMR_0, TMR_1,
WDT_0, and WDT_1 are also stopped. The contents of the CPU registers, several on-chip
peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their
values before transition as long as the prescribed voltage is supplied.
Subsleep mode is cleared by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to
IRQ15, KIN0 to KIN15, or WUE0 to WUE15), RES pin input, or STBY pin input.
When an interrupt occurs, subsleep mode is cleared and interrupt exception handling starts.
In the case of an IRQ0 to IRQ15 interrupt, subsleep mode is not cleared if the corresponding
enable bit has been cleared to 0 or the interrupt has been masked by the CPU. In the case of a
KIN0 to KIN15 or WUE0 to WUE15 interrupt, subsleep mode is not cleared if the input is
disabled or the interrupt has been masked by the CPU. In the case of an interrupt from an on-chip
peripheral module, subsleep mode is not cleared if the interrupt enable register has been set to
disable the reception of that interrupt or the interrupt has been masked by the CPU.
When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with
the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the
RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after
the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev. 3.00 Jul. 14, 2005 Page 876 of 986
REJ09B0098-0300