Figure 5.1 Block Diagram Of Interrupt Controller - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

Section 5 Interrupt Controller

Internal interrupt sources

SWDTEND to IBFI3

: Interrupt control register

: IRQ sense control register

: IRQ enable register

: IRQ status register

: Keyboard matrix interrupt mask register

: Wake-up event interrupt mask register

: System control register

: System control register 3

Rev. 3.00 Jul. 14, 2005 Page 80 of 986

REJ09B0098-0300

INTM1, INTM0

Interrupt controller

Figure 5.1 Block Diagram of Interrupt Controller

Vector number

Priority level

determination

H8s/2100 series H8s/2114r R4f2114r