Sleep Mode; Figure 24.2 Medium-Speed Mode Timing - Renesas H8S Series Hardware Manual

Figure 24.2 shows an example of medium-speed mode timing.
φ ,
peripheral module clock
Bus master clock
Internal address bus
Internal write signal
24.4

Sleep Mode

The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the on-chip peripheral modules do not. The contents of the CPU's internal
registers are retained.
Sleep mode is cleared by any interrupt, the RES pin input, or the STBY pin input.
When an interrupt occurs, sleep mode is cleared and interrupt exception handling starts. Sleep
mode is not cleared if the interrupt is disabled, or interrupts other than NMI have been masked by
the CPU.
When the RES pin is driven low and sleep mode is cleared, a transition is made to the reset state.
After the specified reset input time has elapsed, driving the RES pin high causes the CPU to start
reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
SBYCR

Figure 24.2 Medium-Speed Mode Timing

Section 24 Power-Down Modes
Medium-speed mode
SBYCR
Rev. 3.00 Jul. 14, 2005 Page 871 of 986
REJ09B0098-0300