Renesas H8S Series Hardware Manual page 693

Bit Bit Name Initial Value Slave Host Description
6 IRQ10E3 0
5 IRQ9E3 0
R/W

R/W Host IRQ10 Interrupt Enable 3
Enables or disables an HIRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ10 interrupt request by OBF3A and
IRQE10E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ10 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ10E3 = 0

R/W Host IRQ9 Interrupt Enable 3
Enables or disables an HIRQ9 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ9 interrupt request by OBF3A and IRQE9E3
is disabled
[Clearing conditions]
•
Writing 0 to IRQ9E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ9 interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR3 = 1]
HIRQ9 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ9E3 = 0
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 645 of 986
REJ09B0098-0300