Lmc Control Registers 1 And 2 (Lmccr1 And Lmccr2) - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)

18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2)

LMCCR1 enables/disables the LMC host interface function. LMCCR2 enables/disables interrupts
requested from the host by the interrupt commands and selects wait-state type.
• LMCCR1
Bit Bit Name Initial Value Slave Host Description
7 LMCE 0
6 LPCME 0
5 FWME 0

4 0
Rev. 3.00 Jul. 14, 2005 Page 662 of 986
REJ09B0098-0300
R/W

R/W LPC/FW Memory Cycle Enable
Enables/disables the LPC/FW memory cycles (LPC
memory cycle and FW memory cycle).
0: LPC/FW memory cycles are disabled
1: LPC/FW memory cycles are enabled

R/W LPC Memory Cycle Enable
Enables/disables the LPC memory read/write interface
function. When enabled, data transfer between the
slave (this LSI) and host is performed via the LAD3 to
LAD0, LFRAME, LRESET, and LCLK pins.
0: LPC memory cycles are disabled
1: LPC memory cycles are enabled

R/W Firmware Memory Cycle Enable
Enables/disables the FW memory read/write interface
function. When enabled, data transfer between the
slave (this LSI) and host is performed via the LAD3 to
LAD0, LFRAME, LRESET, and LCLK pins.
0: FW memory cycles are disabled
1: FW memory cycles are enabled

R/W Reserved
This bit cannot be modified.