Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2114R Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2114R R4F2114R Rev.3.00 Revision Date: Jul. 14, 2005...
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Page 3 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 4: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6: Preface
Preface This H8S/2114R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU with Renesas Technology’s original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation.
Page 7 Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2114R Group manuals: Document Title Document No. H8S/2114R Group Hardware Manual...
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Page 9 Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details)  All pages Suffix R is added to group name and product code. • H8S/2114 Group→ H8S/2114R Group • → R4F2114 R4F2114R Appendix Replaced. C. Package Dimensions Figure C.1 Package Dimensions (TFP-144) Rev.
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Page 11: Table Of Contents
Contents Section 1 Overview....................1 Overview..........................1 Internal Block Diagram......................3 Pin Description........................4 1.3.1 Pin Arrangement ....................... 4 1.3.2 Pin Arrangement in Each Operating Mode............... 5 1.3.3 Pin Functions ......................10 Section 2 CPU......................19 Features..........................19 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........20 2.1.2 Differences from H8/300 CPU ................
Page 12 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ........50 2.7.8 Memory Indirect—@@aa:8 ................... 51 2.7.9 Effective Address Calculation ................52 Processing States........................54 Usage Notes ......................... 56 2.9.1 Note on TAS Instruction Usage................56 2.9.2 Note on STM/LDM Instruction Usage ..............56 2.9.3 Note on Bit Manipulation Instructions ..............
Page 13 5.3.3 Break Address Registers A to C (BARA to BARC)..........86 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)....87 5.3.5 IRQ Enable Registers (IER16, IER) ............... 90 5.3.6 IRQ Status Registers (ISR16, ISR) ................. 91 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB)........
Page 14 Section 7 Data Transfer Controller (DTC)............135 Features..........................136 Register Descriptions......................137 7.2.1 DTC Mode Register A (MRA) ................138 7.2.2 DTC Mode Register B (MRB)................139 7.2.3 DTC Source Address Register (SAR)..............139 7.2.4 DTC Destination Address Register (DAR)............140 7.2.5 DTC Transfer Count Register A (CRA) ...............
Page 15 8.1.5 Port 1 Input Pull-Up MOS ..................166 Port 2..........................167 8.2.1 Port 2 Data Direction Register (P2DDR).............. 167 8.2.2 Port 2 Data Register (P2DR)................. 168 8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)........... 168 8.2.4 Pin Functions ......................169 8.2.5 Port 2 Input Pull-Up MOS ..................
Page 16 8.9.2 Port 9 Data Register (P9DR) ................197 8.9.3 Port 9 Pull-Up MOS Control Register (P9PCR)........... 197 8.9.4 Pin Functions ......................198 8.9.5 Port 9 Input Pull-Up MOS ..................200 8.10 Port A..........................201 8.10.1 Port A Data Direction Register (PADDR)............201 8.10.2 Port A Output Data Register (PAODR)..............
Page 17 8.15.1 Port F Data Direction Register (PFDDR) ............. 227 8.15.2 Port F Output Data Register (PFODR) ..............228 8.15.3 Port F Input Data Register (PFPIN)..............228 8.15.4 Pin Functions ......................229 8.15.5 Port F Nch-OD control register (PFNOCR)............231 8.15.6 Pin Functions ......................231 8.15.7 Port F Input Pull-Up MOS..................
Page 18 Section 10 14-Bit PWM Timer (PWMX) ............259 10.1 Features..........................259 10.2 Input/Output Pins....................... 260 10.3 Register Descriptions......................260 10.3.1 PWMX (D/A) Counter (DACNT) ................ 261 10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) ......262 10.3.3 PWMX (D/A) Control Register (DACR) ............. 264 10.3.4 Peripheral Clock Select Register (PCSR) .............
Page 19 11.6 Interrupt Sources........................ 298 11.7 Usage Notes ........................299 11.7.1 Conflict between FRC Write and Clear ..............299 11.7.2 Conflict between FRC Write and Increment............300 11.7.3 Conflict between OCR Write and Compare-Match ..........301 11.7.4 Switching of Internal Clock and FRC Operation ..........302 11.7.5 Module Stop Mode Setting ...................
Page 20 12.8.3 Conflict between TCNT Write and Clear Operations........... 369 12.8.4 Conflict between TCNT Write and Increment Operations ........369 12.8.5 Conflict between TGR Write and Compare Match..........370 12.8.6 Conflict between Buffer Register Write and Compare Match......371 12.8.7 Conflict between TGR Read and Input Capture ........... 372 12.8.8 Conflict between TGR Write and Input Capture ..........
Page 21 13.7.1 16-Bit Count Mode ....................403 13.7.2 Compare-Match Count Mode ................403 13.7.3 Input Capture Operation ..................404 13.8 Interrupt Sources........................ 406 13.9 Usage Notes ........................407 13.9.1 Conflict between TCNT Write and Counter Clear..........407 13.9.2 Conflict between TCNT Write and Count-Up ............408 13.9.3 Conflict between TCOR Write and Compare-Match..........
Page 22 15.3.5 Serial Mode Register (SMR) ................432 15.3.6 Serial Control Register (SCR) ................436 15.3.7 Serial Status Register (SSR) ................. 439 15.3.8 Smart Card Mode Register (SCMR)..............444 15.3.9 Bit Rate Register (BRR) ..................445 15.3.10 Keyboard Comparator Control Register (KBCOMP)........... 453 15.4 Operation in Asynchronous Mode ..................
Page 23 15.10.3 Mark State and Break Sending................498 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..............498 15.10.5 Relation between Writing to TDR and TDRE Flag ..........498 15.10.6 Restrictions on Using DTC................... 499 15.10.7 SCI Operations during Mode Transitions ............. 499 15.10.8 Notes on Switching from SCK Pins to Port Pins ..........
Page 24 17.3.2 Keyboard Buffer Control Register 2 (KBCR2) ............ 587 17.3.3 Keyboard Control Register H (KBCRH) .............. 588 17.3.4 Keyboard Control Register L (KBCRL)............... 590 17.3.5 Keyboard Data Buffer Register (KBBR) .............. 592 17.3.6 Keyboard Buffer Transmit Data Register (KBTR)..........592 17.4 Operation ...........................
Page 25 18.3.14 RAM Buffer Address Register (RBUFAR) ............654 18.3.15 Flash Memory Programming Address Registers H and L (FLWARH and FLARL)..................655 18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register (LMCDIDCR)....................... 656 18.3.17 Erase Block Register (EBLKR) ................657 18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2)........
Page 26 18.4.17 Flash Memory Erasing..................709 18.5 Interrupt Sources........................ 710 18.5.1 IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI ........710 18.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ......711 18.6 Usage Note......................... 714 18.6.1 Data Conflict......................714 18.6.2 Module Stop Mode Setting ................... 715 18.6.3 Operating Mode in LPC/FW Memory Write Cycle..........
Page 27 21.2 Input/Output Pins ....................... 744 21.3 Register Descriptions ......................744 21.3.1 Programming/Erasing Interface Registers ............746 21.3.2 Programming/Erasing Interface Parameters ............753 21.4 On-Board Programming..................... 764 21.4.1 Boot Mode ......................764 21.4.2 User Program Mode....................768 21.4.3 User Boot Mode....................779 21.4.4 Storable Areas for Procedure Program and Program Data ........
Page 28 23.4 Bus Master Clock Select Circuit..................854 23.5 Subclock Input Circuit ....................... 855 23.6 Subclock Waveform Forming Circuit................856 23.7 Clock Select Circuit ......................856 23.8 Handling of X1 and X2 Pins....................857 23.9 Usage Notes ........................857 23.9.1 Notes on Resonator....................857 23.9.2 Notes on Board Design ..................
Page 29 26.3 AC Characteristics ......................955 26.3.1 Clock Timing ......................956 26.3.2 Control Signal Timing ..................958 26.3.3 Timing of On-Chip Peripheral Modules ............... 959 26.3.4 A/D Conversion Characteristics ................971 26.4 Flash Memory Characteristics ................... 972 26.5 Usage Notes ........................973 Appendix ......................975 I/O Port States in Each Pin State..................
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Page 31 Figures Section 1 Overview Figure 1.1 H8S/2114R Group Internal Block Diagram ..............3 Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)............4 Figure 1.3 Sample Design of Reset Signals with no Affection Each Other........17 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..............23 Figure 2.2 Stack Structure in Normal Mode .................
Page 32 Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8)................101 Figure 5.6 Block Diagram of Interrupt Control Operation ............110 Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 ..113 Figure 5.8 State Transition in Interrupt Control Mode 1 ............
Page 33 Figure 10.3 PWMX (D/A) Operation ..................269 Figure 10.4 Output Waveform (OS = 0, DADR corresponds to T ) .......... 272 Figure 10.5 Output Waveform (OS = 1, DADR corresponds to T ) .......... 273 Figure 10.6 D/A Data Register Configuration when CFS = 1 ............ 273 Figure 10.7 Output Waveform when DADR = H'0207 (OS = 1) ..........
Page 34 Figure 12.11 Example of Toggle Output Operation ..............338 Figure 12.12 Example of Input Capture Operation Setting Procedure ........339 Figure 12.13 Example of Input Capture Operation ..............340 Figure 12.14 Example of Synchronous Operation Setting Procedure ........341 Figure 12.15 Example of Synchronous Operation..............342 Figure 12.16 Compare Match Buffer Operation.................
Page 35 Figure 12.51 Conflict between Buffer Register Write and Input Capture ........374 Figure 12.52 Conflict between Overflow and Counter Clearing ..........375 Figure 12.53 Conflict between TCNT Write and Overflow ............376 Section 13 8-Bit Timer (TMR) Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)..........379 Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ..........
Page 36 Figure 15.7 Sample Serial Transmission Flowchart ..............461 Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ............ 462 Figure 15.9 Sample Serial Reception Flowchart (1)..............464 Figure 15.9 Sample Serial Reception Flowchart (2)..............465 Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ..........
Page 37 Figure 15.40 Switching from SCK Pins to Port Pins..............503 Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..504 Section 16 I C Bus Interface (IIC) Figure 16.1 Block Diagram of I C Bus Interface................ 507 Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) ......
Page 38 Figure 16.29 Notes on Reading Master Receive Data ..............573 Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing........................574 Figure 16.31 Stop Condition Issuance Timing ................575 Figure 16.32 IRIC Flag Clearing Timing when WAIT = 1 ............576 Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode......
Page 39 Figure 18.7 Clock Start Request Timing ..................689 Figure 18.8 Example of Command Space Setting ..............692 Figure 18.9 Example of Flash Memory Address Translation ............. 700 Figure 18.10 Example of On-Chip RAM Address Translation ..........701 Figure 18.11 Example 1 of Address Space Priority..............703 Figure 18.12 Example 2 of Address Space Priority..............
Page 40 Figure 21.18 Memory Map in Programmer Mode..............796 Figure 21.19 Boot Program States....................798 Figure 21.20 Bit-Rate-Adjustment Sequence ................799 Figure 21.21 Communication Protocol Format ................800 Figure 21.22 Sequence of New Bit Rate Selection..............811 Figure 21.23 Programming Sequence..................814 Figure 21.24 Erasure Sequence ....................
Page 41 Figure 26.9 I/O Port Input/Output Timing.................. 961 Figure 26.10 FRT Input/Output Timing ..................961 Figure 26.11 FRT Clock Input Timing ..................961 Figure 26.12 TPU Input/Output Timing ..................962 Figure 26.13 TPU Clock Input Timing..................962 Figure 26.14 8-Bit Timer Output Timing ................... 962 Figure 26.15 8-Bit Timer Clock Input Timing ................
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Page 43 Tables Section 1 Overview Table 1.1 H8S/2114R Group Pin Arrangement in Each Operating Mode ........ 5 Table 1.2 Pin Functions ......................10 Section 2 CPU Table 2.1 Instruction Classification ..................35 Table 2.2 Operation Notation ....................36 Table 2.3 Data Transfer Instructions..................37 Table 2.4 Arithmetic Operations Instructions (1) ..............
Page 44 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode) ............ 103 Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) ..................106 Table 5.6 Interrupt Control Modes ..................109 Table 5.7 Interrupts Selected in Each Interrupt Control Mode ..........111 Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode..
Page 45 Section 10 14-Bit PWM Timer (PWMX) Table 10.1 Pin Configuration....................260 Table 10.2 Clock Select of PWMX ..................265 Table 10.3 Reading/Writing to 16-bit Registers ..............267 Settings and Operation (Examples when φ = 20 MHz)......... 270 Table 10.4 Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)....
Page 46 Table 13.2 Clock Input to TCNT and Count Condition (2)............ 387 Table 13.3 Registers Accessible by TMR_X/TMR_Y ............396 Table 13.4 Input Capture Signal Selection ................405 Table 13.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ..406 Table 13.6 Timer Output Priorities..................
Page 47 Section 17 Keyboard Buffer Control Unit (KBU) Table 17.1 Pin Configuration....................584 Section 18 LPC Interface (LPC) Table 18.1 Pin Configuration....................616 Table 18.2 LPC I/O Cycle ...................... 678 Table 18.3 GA20 (P81) Setting/Clearing Timing ..............680 Table 18.4 Fast Gate A20 Output Signals................682 Table 18.5 Scope of LPC Interface Pin Shutdown ..............
Page 48 Table 21.14 Error Code ......................823 Section 22 Boundary Scan (JTAG) Table 22.1 Pin Configuration....................829 Table 22.2 JTAG Register Serial Transfer................830 Table 22.3 Correspondence between Pins and Boundary Scan Register ........ 832 Section 23 Clock Pulse Generator Table 23.1 Damping Resistor Values ..................
Page 49: Section 1 Overview
Section 1 Overview Section 1 Overview Overview • 16-bit high-speed H8S/2000 CPU Upward-compatible with the H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions Data transfer controller (DTC) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit timer pulse unit (TPU) 16-bit free-running timer (FRT)
Page 50: Section 1 Overview
Section 1 Overview Package Code Body Size Pin Pitch TQFP-144 TFP-144 16.0 × 16.0 mm 0.4 mm Rev. 3.00 Jul. 14, 2005 Page 2 of 986 REJ09B0098-0300...
Page 51: Internal Block Diagram
Section 1 Overview Internal Block Diagram PA0/KIN8 PA1/KIN9 PA2/KIN10/PS2AC PA3/KIN11/PS2AD PA4/KIN12/PS2BC Clock pulse H8S/2000CPU PA5/KIN13/PS2BD generator PA6/KIN14/PS2CC PA7/KIN15/PS2CD P20/PW8 P21/PW9 P22/PW10 P23/PW11 XTAL (flash memory) P24/PW12 EXTAL P25/PW13 P26/PW14 P27/PW15 STBY RESO ETRST Interrupt PE0/LID3 controller PE1*/ETCK PE2*/ETDI P30/LAD0 PE3*/ETDO P31/LAD1 PE4*/ETMS P32/LAD2...
Page 52: Pin Description
Section 1 Overview Pin Description 1.3.1 Pin Arrangement 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P74/ExIRQ4/AN4 P73/ExIRQ3/AN3 P72/ExIRQ2/AN2 P71/ExIRQ1/AN1 PB7/WUE7/DLAD0 P70/ExIRQ0/AN0 PB6/WUE6/DLAD1 AVSS...
Page 53: Pin Arrangement In Each Operating Mode
Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 H8S/2114R Group Pin Arrangement in Each Operating Mode Pin No. Pin Name Single-Chip Mode TFP-144 Flash Memory Programmer Mode Mode 2 and Mode 3 (EXPE = 0) P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0...
Page 54 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP-144 Flash Memory Programmer Mode Mode 2 and Mode 3 (EXPE = 0) PE4*/ETMS PE3*/ETDO PE2*/ETDI PE1*/ETCK PE0/LID3 33 (N) PA7/KIN15/PS2CD 34 (N) PA6/KIN14/PS2CC 35 (N) PA5/KIN13/PS2BD 37 (N) PA4/KIN12/PS2BC 38 (N) PA3/KIN11/PS2AD 39 (N) PA2/KIN10/PS2AC...
Page 55 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP-144 Flash Memory Programmer Mode Mode 2 and Mode 3 (EXPE = 0) 58 (N) PG0/ExIRQ8/ExTMCI0 PD7/TIOCB2/TCLKD PD6/TIOCA2 PD5/TIOCB1/TCLKC PD4/TIOCA1 PD3/TIOCD0/TCLKB PD2/TIOCC0/TCLKA PD1/TIOCB0 PD0/TIOCA0 AVSS P70/ExIRQ0/AN0 P71/ExIRQ1/AN1 P72/ExIRQ2/AN2 P73/ExIRQ3/AN3 P74/ExIRQ4/AN4 P75/ExIRQ5/AN5 P76/AN6 P77/AN7 AVCC...
Page 56 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP-144 Flash Memory Programmer Mode Mode 2 and Mode 3 (EXPE = 0) PC6/WUE14/LDRQ PC5/WUE13 PC4/WUE12 PC3/WUE11 PC2/WUE10 PC1/WUE9 PC0/WUE8 P27/PW15 P26/PW14 FA14 P25/PW13 FA13 P24/PW12 FA12 P23/PW11 FA11 P22/PW10 FA10 P21/PW9 P20/PW8 PB7/WUE7/DLAD0...
Page 57 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP-144 Flash Memory Programmer Mode Mode 2 and Mode 3 (EXPE = 0) PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1/IrTxD P85/IRQ4/RxD1/IrRxD 135 (N) P86/IRQ5/SCK1/SCL1 P40/TMCI0/TxD2/DSERIRQ P41/TMO0/RxD2/DCLKRUN...
Page 58: Pin Functions
Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Pin No. Name and Function Power 1, 36, Input Power supply pins. Connect all these pins to the supply system power supply. Connect the bypass capacitor between VCC and VSS (near VCC). Input External capacitance pin for internal step-down power.
Page 59: Electrical Characteristics
Section 1 Overview Type Symbol Pin No. Name and Function Interrupts Input Nonmaskable interrupt request input pin IRQ15 to 17, 19, Input These pins request a maskable interrupt. IRQ0 20, 21, To which pin an IRQ interrupt is input can be selected from the IRQn and ExIRQn pins.
Page 60 Section 1 Overview Type Symbol Pin No. Name and Function PWM timer PW15 to 96 to 103 Output PWM timer pulse output pins. (PWM) From which pin pulses are output can be selected from the PWn and ExPWn pins. ExPW15 to 43 to 46 (n = 15 to 12) ExPW12...
Page 61 Section 1 Overview Type Symbol Pin No. Name and Function 8-bit timer TMRI0 Input External event input pin and counter reset input (TMR_0, TMRI1 TMR_1, TMIX Input External event input pins and counter reset input TMR_X, TMIY pins. To which pin an external event or counter TMR_Y) ExTMIX reset is input can be selected from the TMIn and...
Page 62 Section 1 Overview Type Symbol Pin No. Name and Function KIN15 to Keyboard 33 to 35, Input Matrix keyboard input pins. All pins have a wake- KIN0 up function. Normally, KIN0 to KIN15 function as control 37 to 41, 85 to 78 key scan inputs, and P10 to P17 and P20 to P27 function as key scan outputs.
Page 63 Section 1 Overview Type Symbol Pin No. Name and Function LAD3 to 124 to 121 Input/ Transfer cycle type, address, and data Interface LAD0 Output input/output pins (LPC) LFRAME Input Input pin indicating transfer cycle start and forced termination of an abnormal transfer cycle LRESET Input LPC reset pin.
Page 64 Section 1 Overview Type Symbol Pin No. Name and Function I/O ports P17 to P10 104 to 110, 112 Input/ Eight input/output pins Output P27 to P20 96 to 103 Input/ Eight input/output pins Output P37 to P30 128 to 121 Input/ Eight input/output pins Output...
Page 65: Figure 1.3 Sample Design Of Reset Signals With No Affection Each Other
Section 1 Overview Figure1.3 shows an example of design in which signals for reset do not affect each other. Board edge pin This LSI System reset Power On Reset circuit ETRST ETRST Figure 1.3 Sample Design of Reset Signals with no Affection Each Other Rev.
Page 66 Section 1 Overview Rev. 3.00 Jul. 14, 2005 Page 18 of 986 REJ09B0098-0300...
Page 67: Section 2 Cpu
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16 Mbytes linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
Page 68: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
Section 2 CPU  16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)  32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes  Normal mode  Advanced mode • Power-down state  Transition to power-down state by SLEEP instruction ...
Page 69: Differences From H8/300 Cpu
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers and one 8-bit control register have been added. •...
Page 70: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64 kbytes address space. Advanced mode supports a maximum 16 Mbytes address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal...
Page 71: Figure 2.1 Exception Vector Table (Normal Mode)
Section 2 CPU H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception H'0007 vector table H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) (16 bits) CCR * (16 bits)
Page 72: Advanced Mode
Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers.
Page 73: Figure 2.4 Stack Structure In Advanced Mode
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address.
Page 74: Address Space
Section 2 CPU Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64 kbytes address space in normal mode, and a maximum 16 Mbytes (architecturally 4 Gbytes) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 75: Register Configuration
Section 2 CPU Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. These are classified into two types of registers: general registers and control registers. Control registers refer to a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
Page 76: General Registers
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 77: Program Counter (Pc)
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
Page 78: Condition-Code Register (Ccr)
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 79: Initial Register Values
Section 2 CPU Bit Name Initial Value R/W Description Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: •...
Page 80: Data Formats
Section 2 CPU Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 81: Figure 2.9 General Register Data Formats (2)
Section 2 CPU Data Type Register Number Data Image Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 82: Memory Data Formats
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 83: Instruction Set
Section 2 CPU Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM* , STM* MOVFPE* , MOVTPE* Arithmetic...
Page 84: Table Of Instructions Classified By Function
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register)
Page 85: Table 2.3 Data Transfer Instructions
Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI.
Page 86: Table 2.4 Arithmetic Operations Instructions (1)
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes.
Page 87: Table 2.4 Arithmetic Operations Instructions (2)
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 88: Table 2.5 Logic Operations Instructions
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 89: Table 2.6 Shift Instructions
Section 2 CPU Table 2.6 Shift Instructions Instruction Size* Function Rd (shift) → Rd SHAL B/W/L SHAR Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. Rd (shift) → Rd SHLL B/W/L SHLR Performs a logical shift on data in a general register.
Page 90: Table 2.7 Bit Manipulation Instructions (1)
Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 91: Table 2.7 Bit Manipulation Instructions (2)
Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 92: Table 2.8 Branch Instructions
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨...
Page 93: Table 2.9 System Control Instructions
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR.
Page 94: Table 2.10 Block Data Transfer Instructions
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B – Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: if R4 ≠ 0 then EEPMOV.W – Repeat @ER5+ → @ER6+ R4–1 →...
Page 95: Basic Instruction Formats
Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. •...
Page 96: Addressing Modes And Effective Address Calculation
Section 2 CPU Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes.
Page 97: Register Indirect With Displacement-@(D:16, Ern) Or @(D:32, Ern)
Section 2 CPU 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand.
Page 98: Immediate-#Xx:8, #Xx:16, Or #Xx:32
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24)
Page 99: Memory Indirect-@@Aa:8
Section 2 CPU 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
Page 100: Effective Address Calculation
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper eight bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Page 101: Table 2.13 Effective Address Calculation (2)
Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Rev. 3.00 Jul. 14, 2005 Page 53 of 986 REJ09B0098-0300...
Page 102: Processing States
Section 2 CPU Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 103: Figure 2.13 State Transitions
Section 2 CPU End of bus request Bus request Program execution state SLEEP End of bus instruction request with SLEEP LSON = 0, instruction request SSBY = 0 with LSON = 0, PSS = 0, Bus-released state SSBY = 1 Request for End of exception...
Page 104: Usage Notes
To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, registers ER0, ER1, ER4, and ER5 should be used.
Page 105: Eepmov Instruction
Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4*, which starts from the address indicated by ER5, to the address indicated by ER6. ER5 + R4 ER6 + R4 2.
Page 106 Section 2 CPU Rev. 3.00 Jul. 14, 2005 Page 58 of 986 REJ09B0098-0300...
Page 107: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Operating Mode Selection This LSI supports five operating modes (modes 2 to 4, 6, and 7). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection.
Page 108: Register Descriptions
Section 3 MCU Operating Modes Register Descriptions The following registers are related to the operating modes. For details on the bus control register (BCR), see section 6.2.1, Bus Control Register (BCR). • Mode control register (MDCR) • System control register (SYSCR) •...
Page 109: System Control Register (Syscr)
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space.
Page 110 Section 3 MCU Operating Modes Bit Name Initial Value R/W Description KINWUE R/W Keyboard Control Register Access Enable When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMR), pull-up MOS control register (KMPCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, TCORB_X,...
Page 111: Serial Timer Control Register (Stcr)
Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Name Initial Value R/W Description IICS R/W I C Extra Buffer Select Sets bits 7 to 4 of port A to form an output buffer similar...
Page 112 Section 3 MCU Operating Modes Bit Name Initial Value R/W Description IICE R/W I C Master Enable When the RELOCATE bit is cleared to 0, enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR, and DDCSWR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL), and SCI registers (SMR, BRR, and SCMR).
Page 113 Section 3 MCU Operating Modes Bit Name Initial Value Description FLSHE Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), power-down state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (BCR2, WSCR, PCSR, and SYSCR2).
Page 114: System Control Register 3 (Syscr3)
Section 3 MCU Operating Modes 3.2.4 System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Bit Name Initial Value R/W Description — R/W Reserved The initial value should not be changed. EIVS* R/W Extended interrupt Vector Select* Selects compatible mode or extended mode for the interrupt vector table.
Page 115: Operating Mode Descriptions
Section 3 MCU Operating Modes Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in either advanced mode or single-chip mode. The on-chip ROM is enabled. 3.3.2 Mode 3 The CPU can access a 64-kbyte address space in either normal mode or single-chip mode. The on- chip ROM is enabled.
Page 116: Figure 3.1 Address Map
Section 3 MCU Operating Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Advanced mode Normal mode Single-chip mode Single-chip mode ROM: 1 Mbyte RAM: 8 kbytes ROM: 56 kbytes RAM: 4 kbytes H'0000 H'000000 On-chip ROM On-chip ROM H'DFFF H'0FFFFF H'FF0000...
Page 117: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 118: Exception Sources And Exception Vector Table
Section 4 Exception Handling Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the exception sources and their vector addresses. The EIVS bit in the system control register 3 (SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended vector mode.
Page 119 Section 4 Exception Handling Vector Addresses Vector Exception Source Number Normal Mode Advanced Mode Reserved for system use H'003C to H'003D H'000078 to H'00007B Reserved for system use H'003E to H'003F H'00007C to H'00007F Reserved for system use H'0040 to H'0041 H'000080 to H'000083 External interrupt WUE15 to WUE8 33 H'0042 to H'0043...
Page 120: Table 4.3 Exception Handling Vector Table (Extended Vector Mode)
Section 4 Exception Handling Table 4.3 Exception Handling Vector Table (Extended Vector Mode) Vector Addresses Vector Exception Source Number Normal Mode Advanced Mode Reset H'0000 to H'0001 H'000000 to H'000003 Reserved for system use H'0002 to H'0003 H'000004 to H'000007 ...
Page 121 Section 4 Exception Handling Vector Vector Addresses Number Exception Source Normal Mode Advanced Mode Internal interrupt* H'0044 to H'0045 H'000088 to H'00008B    H'006E to H'006F H'0000DC to H'0000DF External interrupt IRQ8 H'0070 to H'0071 H'0000E0 to H'0000E3 IRQ9 H'0072 to H'0073 H'0000E4 to H'0000E7...
Page 122: Reset
Section 4 Exception Handling Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on.
Page 123: Interrupts Immediately After Reset
Section 4 Exception Handling Vector Internal Prefetch of first fetch processing program instruction φ Internal address bus (1) U (1) L Internal read signal Internal write signal High Internal data bus (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction...
Page 124: Interrupt Exception Handling
Section 4 Exception Handling Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority.
Page 125: Stack Status After Exception Handling
Section 4 Exception Handling Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Advanced mode Normal mode CCR* (16 bits) (24 bits) Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev.
Page 126: Usage Note
Section 4 Exception Handling Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even.
Page 127: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Features • Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks.
Page 128: Figure 5.1 Block Diagram Of Interrupt Controller
Section 5 Interrupt Controller EIVS SYSCR3 INTM1, INTM0 SYSCR NMIEG NMI input NMI input Interrupt request IRQ input IRQ input Vector number Priority level ISCR determination KMIMR WUEMR I, UI KIN input KIN, WUE WUE input input Internal interrupt sources SWDTEND to IBFI3 Interrupt controller Legend:...
Page 129: Input/Output Pins
Section 5 Interrupt Controller Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol Function Input Nonmaskable external interrupt pin Rising edge or falling edge can be selected IRQ15 to IRQ0, Input Maskable external interrupt pins ExIRQ15 to ExIRQ0 Rising-edge, falling-edge, or both-edge detection, or level- sensing, can be selected individually for each pin.
Page 130: Register Descriptions
Section 5 Interrupt Controller Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, System Control Register 3 (SYSCR3). •...
Page 131: Interrupt Control Registers A To D (Icra To Icrd)
Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in tables 5.2 and 5.3. Bit Name Initial Value Description...
Page 132: Table 5.3 Correspondence Between Interrupt Source And Icr (Extended Vector Mode: Eivs = 1)
Section 5 Interrupt Controller Table 5.3 Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1) Register Bit Name ICRA ICRB ICRC ICRD ICRn7 IRQ0 A/D converter — IRQ8 to IRQ11 ICRn6 IRQ1 SCI_1 IRQ12 to IRQ15 ICRn5 IRQ2, IRQ3 —...
Page 133: Address Break Control Register (Abrkcr)
Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested. Bit Name Initial Value Description Undefined Condition Match Flag Address break source flag.
Page 134: Break Address Registers A To C (Bara To Barc)
Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared.
Page 135: Irq Sense Control Registers (Iscr16H, Iscr16L, Iscrh, Iscrl)
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. • ISCR16H Bit Name Initial Value Description IRQ15SCBIR R/WR...
Page 136 Section 5 Interrupt Controller • ISCR16L Bit Name Initial Value Description IRQ11SCB IRQn Sense Control B IRQn Sense Control A IRQ11SCA IRQ10SCB 00: Interrupt request generated at low level of IRQn IRQ10SCA or ExIRQn input IRQ9SCB 01: Interrupt request generated at falling edge of IRQn or ExIRQn input IRQ9SCA IRQ8SCB...
Page 137 Section 5 Interrupt Controller • ISCRH Bit Name Initial Value Description IRQ7SCB IRQn Sense Control B IRQn Sense Control A IRQ7SCA IRQ6SCB 00: Interrupt request generated at low level of IRQn IRQ6SCA or ExIRQn input IRQ5SCB 01: Interrupt request generated at falling edge of IRQn or ExIRQn input IRQ5SCA IRQ4SCB...
Page 138: Irq Enable Registers (Ier16, Ier)
Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. • IER16 Bit Name Initial Value Description IRQ15E IRQn Enable IRQ14E The IRQn interrupt request is enabled when this bit is 1.
Page 139: Irq Status Registers (Isr16, Isr)
Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. • ISR16 Bit Name Initial Value Description IRQ15F R/(W)* [Setting condition] IRQ14F R/(W)* When the interrupt source selected by the ISCR16 registers occurs IRQ13F R/(W)*...
Page 140 Section 5 Interrupt Controller • ISR Bit Name Initial Value Description IRQ7F R/(W)* [Setting condition] IRQ6F R/(W)* When the interrupt source selected by the ISCR registers occurs IRQ5F R/(W)* [Clearing conditions] IRQ4F R/(W)* • When writing 0 to IRQnF flag after reading IRQ3F R/(W)* IRQnF = 1...
Page 141: Keyboard Matrix Interrupt Mask Registers (Kmimra, Kmimr) Wake-Up Event Interrupt Mask Registers (Wuemr, Wuemrb)
Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE0). •...
Page 142 Section 5 Interrupt Controller • WUEMR Bit Name Initial Value Description WUEMR15 Wake-Up Event Interrupt Mask WUEMR14 These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). WUEMR13 0: Enables a wake-up event input interrupt request WUEMR12 1: Disables a wake-up event input interrupt request WUEMR11...
Page 143: Figure 5.2 Relation Between Irq7 And Irq6 Interrupts, Kin15 To Kin0 Interrupts
Section 5 Interrupt Controller KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) IRQ6 internal P65/KIN5 Edge-level selection signal IRQ6 interrupt enable/disable KMIMR6 (Initial value of 0) circuit P66/KIN6/IRQ6 KMIMR7 (Initial value of 1) P67/KIN7/IRQ7 ISS7 P42/ExIRQ7 KMIMR8 (Initial value of 1) IRQ7 internal PA0/KIN8 Edge-level selection...
Page 144: Figure 5.3 Relation Between Irq7 And Irq6 Interrupts, Kin15 To Kin0 Interrupts, Wue7 To Wue0 Interrupts, Kmimr, Kmimra, And Wuemrb (Extended Vector Mode: Eivs = 1)
Section 5 Interrupt Controller KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) KIN internal P65/KIN5 signal KIN interrupt Falling-edge detection circuit (KIN7 to KIN0) KMIMR6 (Initial value of 1) P66/KIN6/IRQ6 P52/ExIRQ6 Edge-level selection enable/disable IRQ6 interrupt KMIMR7 (Initial value of 1) circuit P67/KIN7/IRQ7 Edge-level selection...
Page 145: Irq Sense Port Select Register 16 (Issr16), Irq Sense Port Select Register (Issr)
Section 5 Interrupt Controller 5.3.8 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from IRQ15 to IRQ0 pins and ExIRQ15 to ExIRQ0 pins. • ISSR16 Bit Name Initial Value Description...
Page 146 Section 5 Interrupt Controller • ISSR Bit Name Initial Value R/W Description ISS7 R/W 0: P67/IRQ7 is selected 1: P42/ExIRQ7 is selected  R/W Reserved The initial values should not be changed. ISS5 R/W 0: P86/IRQ5 is selected 1: P75/ExIRQ5 is selected ISS4 R/W 0: P85/IRQ4 is selected 1: P74/ExIRQ4 is selected...
Page 147: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources 5.4.1 External Interrupt Sources The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Page 148: Figure 5.4 Block Diagram Of Interrupts Irq15 To Irq0
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF IRQn IRQn interrupt Edge/level request ISSm detection circuit ExIRQn Clear signal n = 15 to 0 m = 15 to 7 and 5 to 0 Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit in SYSCR3. Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0 KIN15 to KIN0 Interrupts and WUE15 to WUE0 Interrupts Interrupts KIN15 to KIN0 and WUE15 to WUE0 are requested by an input signal at pins KIN15...
Page 149: Figure 5.5 Block Diagram Of Interrupts Kin15 To Kin0 And Wue15 To Wue0 (Example Of Wue15 To Wue8)
Section 5 Interrupt Controller • Extended vector mode (EIVS = 1 in SYSCR3)  Interrupts KIN15 to KIN8, KIN7 to KIN0, WUE15 to WUE8, and WUE7 to WUE0 each form a group. The interrupt exception handling for an interrupt request from the same group is started at the same vector address.
Page 150: Internal Interrupt Sources
Section 5 Interrupt Controller 5.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller.
Page 151: Table 5.4 Interrupt Sources, Vector Addresses, And Interrupt Priorities (H8S/2140B Group Compatible Vector Mode)
Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode) Vector Address Origin of Interrupt Vector Normal Advanced Source Name Number Mode Mode Priority External pin H'000E H'00001C — High IRQ0 H'0020 H'000040 ICRA7 IRQ1...
Page 152 Section 5 Interrupt Controller Vector Address Origin of Interrupt Vector Normal Advanced Source Name Number Mode Mode Priority TPU_2 TGI2A (TGR2A input H'0056 H'0000AC ICRD1 High capture/compare match) TGI2B (TGR2B input H'0058 H'0000B0 capture/compare match) TGI2V (Overflow 2) H'005A H'0000B4 TGI2U (Underflow 2) H'005C H'0000B8...
Page 153 Section 5 Interrupt Controller Vector Address Origin of Interrupt Vector Normal Advanced Source Name Number Mode Mode Priority SCI_2 ERI2 (Reception error 2) H'00B0 H'000160 ICRC5 High RXI2 (Reception completion 2) H'00B2 H'000164 TXI2 (Transmission data empty 2) H'00B4 H'000168 TEI2 (Transmission end 2) H'00B6 H'00016C...
Page 154: Table 5.5 Interrupt Sources, Vector Addresses, And Interrupt Priorities (Extended Vector Mode)
Section 5 Interrupt Controller Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) Vector Address Origin of Interrupt Vector Normal Advanced Source Name Number Mode Mode Priority External pin H'000E H'00001C — High IRQ0 H'0020 H'000040 ICRA7 IRQ1 H'0022 H'000044...
Page 155 Section 5 Interrupt Controller Vector Address Origin of Interrupt Vector Normal Advanced Source Name Number Mode Mode Priority TPU_2 TGI2A (TGR2A input H'0056 H'0000AC ICRD1 High capture/compare match) TGI2B (TGR2B input H'0058 H'0000B0 capture/compare match) TGI2V (Overflow 1) H'005A H'0000B4 TGI2U (Underflow 2) H'005C H'0000B8...
Page 156 Section 5 Interrupt Controller Vector Address Origin of Interrupt Vector Normal Advanced Source Name Number Mode Mode Priority SCI_1 ERI1 (Reception error 1) H'00A8 H'000150 ICRC6 High RXI1 (Reception completion 1) H'00AA H'000154 TXI1 (Transmission data empty 1) H'00AC H'000158 TEI1 (Transmission end 1) H'00AE H'00015C...
Page 157: Interrupt Control Modes And Interrupt Operation
Section 5 Interrupt Controller Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR.
Page 158: Figure 5.6 Block Diagram Of Interrupt Control Operation
Section 5 Interrupt Controller Figure 5.6 shows a block diagram of the priority determination circuit. Interrupt Default priority acceptance control Interrupt Vector determination source number and 3-level mask control Interrupt control modes 0 and 1 Figure 5.6 Block Diagram of Interrupt Control Operation Rev.
Page 159: Table 5.7 Interrupts Selected In Each Interrupt Control Mode
Section 5 Interrupt Controller (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.7 shows the interrupts selected in each interrupt control mode.
Page 160: Interrupt Control Mode 0
Section 5 Interrupt Controller Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Setting Control Interrupt Default Priority 3-Level Control Control Mode INTM1 INTM0 Determination Ο Ο — Ο Ο [Legend] Ο: Interrupt operation control is performed Used as an interrupt mask bit Priority is set —:...
Page 161: Figure 5.7 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 0
Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Hold pending An interrupt with interrupt...
Page 162: Interrupt Control Mode 1
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. •...
Page 163 Section 5 Interrupt Controller Figure 5.9 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Page 164: Figure 5.9 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 1
Section 5 Interrupt Controller Program execution state Interrupt generated? Hold pending An interrupt with interrupt control level 1? IRQ0 IRQ0 IRQ1 IRQ1 IBFI3 IBFI3 I = 0 I = 0 UI = 0 Save PC and CCR 1, UI Read vector address Branch to interrupt handling routine Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev.
Page 165: Interrupt Exception Handling Sequence
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Page 166: Figure 5.10 Interrupt Exception Handling
Section 5 Interrupt Controller Figure 5.10 Interrupt Exception Handling Rev. 3.00 Jul. 14, 2005 Page 118 of 986 REJ09B0098-0300...
Page 167: Interrupt Response Times
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.9 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.9 Interrupt Response Times Execution Status Normal Mode Advanced Mode Interrupt priority determination*...
Page 168: Dtc Activation By Interrupt
Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details on interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC).
Page 169: Table 5.10 Interrupt Source Selection And Clearing Control
Section 5 Interrupt Controller Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.4, Location of Register Information and DTC Vector Table, for the respective priorities. Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling.
Page 170: Address Breaks
Section 5 Interrupt Controller Address Breaks 5.7.1 Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed.
Page 171: Operation
Section 5 Interrupt Controller 5.7.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority.
Page 172: Figure 5.13 Examples Of Address Break Timing
Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal Vector Internal Instruction fetch fetch fetch fetch fetch operation fetch operation fetch Stack save φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318...
Page 173: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 174: Instructions For Disabling Interrupts
Section 5 Interrupt Controller 5.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 175: External Interrupt Pin In Software Standby Mode And Watch Mode
Section 5 Interrupt Controller 5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode • When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ0, KIN15 to KIN0, and WUE15 to WUE0) are used as external input pins in software standby mode or watch mode, the pins should not be left floating.
Page 176 Section 5 Interrupt Controller Rev. 3.00 Jul. 14, 2005 Page 128 of 986 REJ09B0098-0300...
Page 177: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC). The BSC has a bus arbitration function, and controls the operation of the internal bus masters – CPU, data transfer controller (DTC), and LPC interface (LPC). Though this LSI does not have external extended functions, take care not to set inappropriate values in the control registers related to the bus controller when utilizing software with other similar products.
Page 178: Register Descriptions
Section 6 Bus Controller (BSC) Register Descriptions The bus controller has the following registers. • Bus control register (BCR) • Wait state control register (WSCR) 6.2.1 Bus Control Register (BCR) Bit Name Initial Value Description — Reserved The initial value should not be changed. ICIS0 Idle Cycle Insertion The initial value should not be changed.
Page 179: Wait State Control Register (Wscr)
Section 6 Bus Controller (BSC) 6.2.2 Wait State Control Register (WSCR) Bit Name Initial Value Description — Reserved — The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed. WMS1 Wait Mode Select 1, 0 WMS0...
Page 180: Bus Arbitration
Section 6 Bus Controller (BSC) Bus Arbitration The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters – CPU, DTC, and LPC – which perform read/write operations when they have possession of the bus. 6.3.1 Priority of Bus Masters Each bus master requests the bus by means of a bus request signal.
Page 181 Section 6 Bus Controller (BSC) The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC is a bus master with lower priority than the LPC, and if a bus request is received from the LPC, the bus arbiter transfers the bus to the LPC.
Page 182 Section 6 Bus Controller (BSC) Rev. 3.00 Jul. 14, 2005 Page 134 of 986 REJ09B0098-0300...
Page 183: Section 7 Data Transfer Controller (Dtc)
Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on- chip RAM.
Page 184: Features
Section 7 Data Transfer Controller (DTC) Features • Transfer is possible over any number of channels • Three transfer modes Normal, repeat, and block transfer modes are available • One activation source can trigger a number of data transfers (chain transfer) •...
Page 185: Register Descriptions
Section 7 Data Transfer Controller (DTC) Register Descriptions The DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) •...
Page 186: Dtc Mode Register A (Mra)
Section 7 Data Transfer Controller (DTC) 7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Name Initial Value R/W Description Undefined — Source Address Mode 1, 0 Undefined — These bits specify an SAR operation after a data transfer. 0*: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1)
Page 187: Dtc Mode Register B (Mrb)
Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Name Initial Value Description CHNE Undefined — DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed.
Page 188: Dtc Destination Address Register (Dar)
Section 7 Data Transfer Controller (DTC) 7.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
Page 189: Dtc Enable Registers (Dtcer)
Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers (DTCER) DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 and 7.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR.
Page 190: Dtc Vector Register (Dtvecr)
Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can always be written to this bit.
Page 191: Activation Sources
Section 7 Data Transfer Controller (DTC) Activation Sources The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared.
Page 192: Location Of Register Information And Dtc Vector Table
Section 7 Data Transfer Controller (DTC) Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3.
Page 193: Table 7.2 Interrupt Sources, Dtc Vector Addresses, And Corresponding Dtces
Section 7 Data Transfer Controller (DTC) Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Vector DTC Vector Source Origin Activation Source Number Address DTCE* Priority Software Write to DTVECR DTVECR H'0400 + (vector — High number x 2) External pins IRQ0 H'0420...
Page 194 Section 7 Data Transfer Controller (DTC) Activation Vector DTC Vector Source Origin Activation Source Number Address DTCE* Priority ERRI H'04D8 DTCEE3 High IBFI1 H'04DA DTCEE2 IBFI2 H'04DC DTCEE1 IBFI3 H'04DE DTCEE0 Note: DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0.
Page 195: Operation
Section 7 Data Transfer Controller (DTC) Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
Page 196: Normal Mode
Section 7 Data Transfer Controller (DTC) 7.5.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt can be requested.
Page 197: Repeat Mode
Section 7 Data Transfer Controller (DTC) 7.5.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.4 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has been completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated.
Page 198: Block Transfer Mode
Section 7 Data Transfer Controller (DTC) 7.5.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.5 lists the register functions in block transfer mode.
Page 199: Chain Transfer
Section 7 Data Transfer Controller (DTC) 7.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Page 200: Interrupt Sources
Section 7 Data Transfer Controller (DTC) 7.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated.
Page 201: Figure 7.10 Dtc Operation Timing (Example Of Block Transfer Mode, With Block Size Of 2)
Section 7 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information Transfer information read write Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ...
Page 202: Number Of Dtc Execution States
Section 7 Data Transfer Controller (DTC) 7.5.7 Number of DTC Execution States Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number of states required for each execution status. Table 7.6 DTC Execution Status Register Information Internal...
Page 203: Procedures For Using Dtc
Section 7 Data Transfer Controller (DTC) The number of execution states is calculated from using the formula below. Note that Σ is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1).
Page 204: Examples Of Use Of The Dtc
Section 7 Data Transfer Controller (DTC) Examples of Use of the DTC 7.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
Page 205: Software Activation
Section 7 Data Transfer Controller (DTC) 7.7.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000.
Page 206: Usage Notes
Section 7 Data Transfer Controller (DTC) Usage Notes 7.8.1 Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop mode is set.
Page 207: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Table 8.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and data registers (DR and ODR) that store output data.
Page 208 Section 8 I/O Ports Port Description Mode 2, Mode 3 I/O Status Port 3 General I/O port also P37/SERIRQ Built-in input pull-up MOSs functioning as LPC P36/LCLK LED drive capability input/output P35/LRESET (sink current 5 mA) P34/LFRAME P33/LAD3 P32/LAD2 P31/LAD1 P30/LAD0 Port 4 General I/O port also...
Page 209 Section 8 I/O Ports Port Description Mode 2, Mode 3 I/O Status Port 7 General input port also P77/AN7 functioning as interrupt P76/AN6 input and A/D converter P75/ExIRQ5/AN5 analog input P74/ExIRQ4/AN4 P73/ExIRQ3/AN3 P72/ExIRQ2/AN2 P71/ExIRQ1/AN1 P70/ExIRQ0/AN0 Port 8 General I/O port also P86/IRQ5/SCK1/SCL1 functioning as interrupt P85/IRQ4/RxD1/IrRxD...
Page 210 Section 8 I/O Ports Port Description Mode 2, Mode 3 I/O Status Port B General I/O port also Built-in input pull-up MOSs PB7/WUE7/DLAD0 functioning as wake-up PB6/WUE6/DLAD1 event input and LPC input/output PB5/WUE5/DLAD2 PB4/WUE4/DLAD3 PB3/WUE3/DLFRAME PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI Port C General I/O port also PC7/WUE15/DLDRQ Built-in input pull-up MOSs and...
Page 211 Section 8 I/O Ports Port Description Mode 2, Mode 3 I/O Status Port F General I/O port also Built-in input pull-up MOSs PF7/ExPW15 functioning as interrupt PF6/ExPW14 input, and PWM and TMR_X outputs PF5/ExPW13 PF4/ExPW12 PF3/IRQ11/ExTMOX PF2/IRQ10 PF1/IRQ9 PF0/IRQ8 Port G General I/O port also Built-in noise canceller PG7/ExIRQ15/ExSCLB interrupt input, TMR_0,...
Page 212: Port 1
Section 8 I/O Ports Port 1 Port 1 is an 8-bit I/O port. Port 1 has a built-in input pull-up MOS that can be controlled by software. Port 1 has the following registers. • Port 1 data direction register (P1DDR) •...
Page 213: Port 1 Data Register (P1Dr)
Section 8 I/O Ports 8.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Name Initial Value Description P17DR P1DR stores output data for the port 1 pins that are used as the general output port. P16DR If a port 1 read is performed while the P1DDR bits P15DR...
Page 214: Pin Functions
Section 8 I/O Ports 8.1.4 Pin Functions • P17, P16, P15, P14, P13, P12, P11, P10 The function of port 1 pins is switched as shown below according to the P1nDDR bit. P1nDDR Pin function P1n input pin P1n output pin Note: n = 7 to 0 8.1.5 Port 1 Input Pull-Up MOS...
Page 215: Port 2
Section 8 I/O Ports Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also functions as PWM output pins. Port 2 has a built-in input pull-up MOS that can be controlled by software. Port 2 has the following registers. •...
Page 216: Port 2 Data Register (P2Dr)
Section 8 I/O Ports 8.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Name Initial Value Description P27DR P2DR stores output data for the port 2 pins that are used as the general output port. P26DR If a port 2 read is performed while the P2DDR bits P25DR...
Page 217: Pin Functions
Section 8 I/O Ports 8.2.4 Pin Functions • P27/PW15, P26/PW14 The function of port 2 pins is switched as shown below according to the combination of the PWMAS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the P2nDDR bit. PWMAS P2nDDR ...
Page 218: Port 2 Input Pull-Up Mos
Section 8 I/O Ports 8.2.5 Port 2 Input Pull-Up MOS Port 2 has a built-in input pull-up MOS that can be controlled by software. Table 8.3 summarizes the input pull-up MOS states. Table 8.3 Port 2 Input Pull-Up MOS States Hardware Standby Software Standby Reset...
Page 219: Port 3
Section 8 I/O Ports Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as LPC input/output pins. Port 3 has a built-in input pull-up MOS that can be controlled by software. Port 3 has the following registers. •...
Page 220: Port 3 Data Register (P3Dr)
Section 8 I/O Ports 8.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Name Initial Value Description P37DR P3DR stores output data for the port 3 pins that are used as the general output port. P36DR If a port 3 read is performed while the P3DDR bits P35DR...
Page 221: Pin Functions
Section 8 I/O Ports 8.3.4 Pin Functions • P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The function of port 3 pins is switched as shown below according to the combination of the LPC4E bit in HICR4 of LPC, LPC3E to LPC1E bits in HICR0, LMCE bit in LMCCR1, and the P3nDDR bit.
Page 222: Port 4
Section 8 I/O Ports Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as interrupt input, PWMX output, TMR_0, TMR_1, SCI_2, IIC_1, and LPC input/output pins. The output format for P42 and SCK2 is NMOS push-pull output. The output format for SDA1 is NMOS open-drain output. Port 4 has the following registers.
Page 223: Port 4 Data Register (P4Dr)
Section 8 I/O Ports 8.4.2 Port 4 Data Register (P4DR) P4DR stores output data for the port 4 pins. Bit Name Initial Value Description P47DR P4DR stores output data for the port 4 pins that are used as the general output port. P46DR If a port 4 read is performed while the P4DDR bits P45DR...
Page 224 Section 8 I/O Ports • P45/TMRI1 The pin function is switched as shown below according to the P45DDR bit. When the CCLR1 and CCLR0 bits in TCR of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. P45DDR Pin function P45 input pin...
Page 225 Section 8 I/O Ports IICENABLE CKE1    CKE0     P42DDR Pin function P42 input P42 output SCK2 output SCK2 output SCK2 input SDA1 input/output ExIRQ7 input pin/TMRI0 input pin Note: To use this pin as the SDA1 input/output pin, clear the SDA1AS and SDA1BS bits in PTCNT1, CKE1 and CKE0 bits in SCR of SCI_2, and C/A bit in SMR to 0.
Page 226: Port 5
Section 8 I/O Ports Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as interrupt input pins, IIC_0 input/output pin, TMR_Y output pin, and the external sub-clock input pin. The output format for P52 is NMOS push-pull output.
Page 227: Pin Functions
Section 8 I/O Ports 8.5.3 Pin Functions • P52/ExIRQ6/SCL0 The pin function is switched as shown below according to the combination of the SCL0AS and SCL0BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P52DDR bit. When the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the ExIRQ6 interrupt input pin.
Page 228: Port 6
Section 8 I/O Ports Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as the interrupt input pin, TMR_Y, keyboard and noise cancel input pins, FRT, and TMR_X input/output pin. Port 6 can change the input level for four levels.
Page 229: Port 6 Data Register (P6Dr)
Section 8 I/O Ports 8.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Name Initial Value Description P67DR P6DR stores output data for the port 6 pins that are used as the general output port. P66DR If a port 6 read is performed while the P6DDR bits P65DR...
Page 230: Noise Canceller Enable Register (P6Nce)
Section 8 I/O Ports 8.6.4 Noise Canceller Enable Register (P6NCE) P6NCE enables or disables the noise cancel circuit at port 6. Bit Name Initial Value Description P67NCE Noise cancel circuit is enabled when P6NCE bit is set to 1, and the pin state is fetched in the P6DR in P66NCE the sampling cycle set by the P6NCCS.
Page 231: Noise Cancel Cycle Setting Register (P6Nccs)
Section 8 I/O Ports 8.6.6 Noise Cancel Cycle Setting Register (P6NCCS) P6NCCS controls the sampling cycles of the noise canceller. Bit Name Initial Value Description 7 to 3  Undefined Reserved The read data is undefined. The write value should always be 0.
Page 232: Figure 8.1 Noise Cancel Circuit
Section 8 I/O Ports φ/2, φ/32, φ/8192, φ/16384, φ/32768, φ/65536, φ/131072, φ/262144 Sampling clock selection Latch Latch Latch Latch input Port data register Interrupt input Key board input Sampling clock Figure 8.1 Noise Cancel Circuit P6n Input 1 expected P6n Input 0 expected P6n Input (n = 7 to 0)
Page 233: System Control Register 2 (Syscr2)
Section 8 I/O Ports 8.6.7 System Control Register 2 (SYSCR2) SYSCR2 controls the port 6 input level selection and the current specifications for the port 6 input pull-up MOSs. Bit Name Initial Value Description KWUL1 Key Wakeup Level 1, 0 KWUL0 Select the port 6 input level.
Page 234 Section 8 I/O Ports • P66/IRQ6/KIN6/FTOB The function of port 6 pins is switched as shown below according to the combination of the OEB bit in TOCR of FRT and the P66DDR bit. When the KMIMR6 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN6 input pin.
Page 235 Section 8 I/O Ports • P63/KIN3/FTIB The function of port 6 pins is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. When the KMIMR3 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN3 input pin.
Page 236: Port 6 Input Pull-Up Mos
Section 8 I/O Ports • P60/KIN0/FTCI/TMIX The function of port 6 pins is switched as shown below according to the P60DDR bit. When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can be used as the FTCI input pin.
Page 237: Port 7
Section 8 I/O Ports Port 7 Port 7 is an 8-bit input port. Port 7 pins also function as the interrupt input pins and A/D converter analog input pins. Port 7 has the following register. • Port 7 input data register (P7PIN) 8.7.1 Port 7 Input Data Register (P7PIN) P7PIN indicates the pin states.
Page 238: Pin Functions
Section 8 I/O Ports 8.7.2 Pin Functions • P77/AN7, P76/AN6 Pin function P7n input pin/ANn input pin Note: n = 7, 6 • P75/ExIRQ5/AN5, P74/ExIRQ4/AN4, P73/ExIRQ3/AN3, P72/ExIRQ2/AN2, P71/ExIRQ1/AN1, P70/ExIRQ0/AN0 When the ISS0n bit in ISSR and the IRQnE bit in IER of the interrupt controller are set to 1, this pin can be used as the ExIRQn interrupt input pin.
Page 239: Port 8
Section 8 I/O Ports Port 8 Port 8 is a 7-bit I/O port. Port 8 pins also function as the interrupt input pins, SCI_1 and IIC_1 input/output pins, and LPC input/output pin. The output format for P86 and SCK1 is NMOS push- pull output.
Page 240: Port 8 Data Register (P8Dr)
Section 8 I/O Ports 8.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Name Initial Value Description   Reserved The initial value should not be changed. P86DR P8DR stores output data for the port 8 pins that are used as the general output port.
Page 241: Pin Functions
Section 8 I/O Ports 8.8.3 Pin Functions • P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the SCL1AS and SCL1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, C/A bit in SMR of SCI_1, CKE0 and CKE1 bits in SCR, and the P86DDR bit.
Page 242 Section 8 I/O Ports • P84/IRQ3/TxD1/IrTxD The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P84DDR bit. When the ISS3 bit in ISSR is cleared to 0 and the IRQ3E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ3 input pin.
Page 243 Section 8 I/O Ports • P81/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 of LPC and the P81DDR bit. FGA20E  P81DDR Pin function P81 input pin P81 output pin GA20 output pin •...
Page 244: Port 9
Section 8 I/O Ports Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, A/D converter inputs, sub-clock input pin, IIC_0 I/O pin, and the system clock output pin (φ). The output format for P97 is NMOS push-pull output.
Page 245: Port 9 Data Register (P9Dr)
Section 8 I/O Ports 8.9.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit Name Initial Value Description P97DR P9DR stores output data for the port 9 pins that are used as the general output port except for bit 6. P96DR Undefined* If a port 9 read is performed while the P9DDR bits...
Page 246: Pin Functions
Section 8 I/O Ports 8.9.4 Pin Functions • P97/IRQ15/SDA0 The pin function is switched as shown below according to the combination of the SDA0AS and SDA0BS bits in PTCNT1, ICE bit in ICCR of IIC_0, and the P97DDR bit. When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ15 input pin.
Page 247 Section 8 I/O Ports • P94/IRQ13 The pin function is switched as shown below according to the P94DDR bit. When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ13 input pin.
Page 248: Port 9 Input Pull-Up Mos
Section 8 I/O Ports • P90/IRQ2/ADTRG The pin function is switched as shown below according to the P90DDR bit. When the TRGS1 and TRGS0 bits in ADCR are both set to 1, this pin can be used as the ADTRG input pin. When the ISS2 bit in ISSR is cleared to 0 and the IRQ2E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ2 input pin.
Page 249: Port A
Section 8 I/O Ports 8.10 Port A Port A is an 8-bit I/O port. Port A pins also function as the keyboard input pins and KBU input/output pins. The output format for port A is NMOS push-pull output. Port A has the following registers. PADDR and PAPIN have the same address. •...
Page 250: Port A Output Data Register (Paodr)
Section 8 I/O Ports 8.10.2 Port A Output Data Register (PAODR) PAODR stores output data for the port A pins. Bit Name Initial Value Description PA7ODR PAODR stores output data for the port A pins that are used as the general output port. PA6ODR PA5ODR PA4ODR...
Page 251: Pin Functions
Section 8 I/O Ports 8.10.4 Pin Functions • PA7/KIN15/PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN12/PS2BC, PA3/KIN11/PS2AD, PA2/KIN10/PS2AC The function of port A pins is switched according to the combination of the KBIOE bit in KBCRH of KBU and the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KINm input pin.
Page 252: Port B
Section 8 I/O Ports 8.11 Port B Port B is an 8-bit I/O port. Port B pins also function as the wake-up event input pins and LPC input/output pins. Port B has the following registers. PBDDR and PBPIN have the same address. •...
Page 253: Port B Output Data Register (Pbodr)
Section 8 I/O Ports 8.11.2 Port B Output Data Register (PBODR) PBODR stores output data for the port B pins. Bit Name Initial Value Description PB7ODR The PBODR register stores the output data for the pins that are used as the general output port. PB6ODR PB5ODR PB4ODR...
Page 254: Pin Functions
Section 8 I/O Ports 8.11.4 Pin Functions • PB7/WUE7/DLAD0 The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB7DDR bit. When the WUEM7 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE7 input pin.
Page 255 Section 8 I/O Ports • PB4/WUE4/DLAD3 The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB4DDR bit. When the WUEM4 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE4 input pin. LPCS ...
Page 256: Port B Input Pull-Up Mos
Section 8 I/O Ports • PB1/ WUE1/LSCI The pin function is switched as shown below according to the combination of the LSCIE bit in HICR0 of LPC and the PB1DDR bit. When the WUEM1 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE1 input pin.
Page 257: Port C
Section 8 I/O Ports 8.12 Port C Port C is an 8-bit I/O port. Port C pins also function as the wake-up event inputs, noise cancel input pins, and LPC input/output pins. Port C has the following registers. PCDDR and PCPIN have the same address.
Page 258: Port C Output Data Register (Pcodr)
Section 8 I/O Ports 8.12.2 Port C Output Data Register (PCODR) PCODR stores output data for the port C pins. Bit Name Initial Value Description PC7ODR The PCODR register stores the output data for the pins that are used as the general output port. PC6ODR PC5ODR PC4ODR...
Page 259: Noise Canceller Enable Register (Pcnce)
Section 8 I/O Ports 8.12.4 Noise Canceller Enable Register (PCNCE) PCNCE enables or disables the noise cancel circuit at port C. Bit Name Initial Value Description PC7NCE Noise cancel circuit is enabled when PCNCE bit is set to 1, and the pin state is fetched in the PCPIN PC6NCE in the sampling cycle set by the PCNCCS.
Page 260: Noise Cancel Cycle Setting Register (Pcnccs)
Section 8 I/O Ports 8.12.6 Noise Cancel Cycle Setting Register (PCNCCS) PCNCCS controls the sampling cycles of the noise canceller. Bit Name Initial Value Description 7 to 3  Undefined Reserved The read data is undefined. The initial value should not be changed.
Page 261 Section 8 I/O Ports • PC6/WUE14/LDRQ The pin function is switched as shown below according to the combination of the LDRQS bit in PTCNT2 and the PC6DDR. When the WUEMR14 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE14 input pin. LDRQS ...
Page 262 Section 8 I/O Ports • PC2/WUE10 The pin function is switched as shown below according to the PC2DDR. When the WUEMR10 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE10 input pin. PC2DDR Pin Function PC2 input pin...
Page 263: Port C Nch-Od Control Register (Pcnocr)
Section 8 I/O Ports 8.12.8 Port C Nch-OD control register (PCNOCR) The individual bits of PCNOCR specify output driver type for the pins of port C that is specified to output. Bit Name Initial Value Description PC7NOCR 0: CMOS (P channel driver is enable) PC6NOCR 1: N channel open-drain PC5NOCR...
Page 264: 8.12.10 Port C Input Pull-Up Mos
Section 8 I/O Ports 8.12.10 Port C Input Pull-Up MOS Port C has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.8 summarizes the input pull-up MOS states.
Page 265: Port D
Section 8 I/O Ports 8.13 Port D Port D is an 8-bit I/O port. Port D pins also function as the TPU I/O pins. Port D has the following registers. PDDDR and PDPIN have the same address. • Port D data direction register (PDDDR) •...
Page 266: Port D Output Data Register (Pdodr)
Section 8 I/O Ports 8.13.2 Port D Output Data Register (PDODR) PDODR stores output data for the port D pins. Bit Name Initial Value Description PD7ODR The PDODR register stores the output data for the pins that are used as the general output port. PD6ODR PD5ODR PD4ODR...
Page 267: Pin Functions
Section 8 I/O Ports 8.13.4 Pin Functions • PD7/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 setting, TPSC2 to TPSC0 bits in TCR_0 of TPU, and the PD7DDR. TPU Channel 2 Input or Initial Value Output Setting...
Page 268 Section 8 I/O Ports • PD5/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting, TPSC2 to TPSC0 bits in TCR_0 and TCR_2 of TPU, and the PD5DDR. TPU Channel 1 Input or Initial Value Output Setting...
Page 269 Section 8 I/O Ports • PD3/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 setting, TPSC2 to TPSC0 bits in TCR_0 to TCR_2 of TPU, and the PD3DDR. TPU Channel 0 Input or Initial Value Output Setting...
Page 270 Section 8 I/O Ports • PD1/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting and the PD1DDR. TPU Channel 0 Input or Initial Value Output Setting  PD1DDR Pin Function PD1 input pin PD1 output pin TIOCB0 output pin...
Page 271: Port D Nch-Od Control Register (Pdnocr)
Section 8 I/O Ports 8.13.5 Port D Nch-OD control register (PDNOCR) The individual bits of PDNOCR specify output driver type for the pins of port D that is specified to output. Bit Name Initial Value Description PD7NOCR 0: CMOS (P channel driver is enable) PD6NOCR 1: N channel open-drain PD5NOCR...
Page 272: Port D Input Pull-Up Mos
Section 8 I/O Ports 8.13.7 Port D Input Pull-Up MOS Port D has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.9 summarizes the input pull-up MOS states.
Page 273: Port E
Section 8 I/O Ports 8.14 Port E Port E is a 5-bit input port. Port E pins also function as the LPC input pins and emulator input/output pins. Port E has the following registers. • Port E input pull-up MOS control register (PEPCR) •...
Page 274: Pin Functions
Section 8 I/O Ports 8.14.3 Pin Functions • PE4, PE3, PE2, PE1 The pin function is switched as shown below according to the PEnDDR. Pin Function PEn input pin Note: n = 4 to 1 The PE5 to PE1 pins are not supported in the system development tool (emulator). •...
Page 275: Port F
Section 8 I/O Ports 8.15 Port F Port F is an 8-bit I/O port. Port F pins also function as the interrupt input pins and TMR_X and PWM output pins. Port F has the following registers. PFDDR and PFPIN have the same address. •...
Page 276: Port F Output Data Register (Pfodr)
Section 8 I/O Ports 8.15.2 Port F Output Data Register (PFODR) PFODR stores output data for the port F pins. Bit Name Initial Value Description PF7ODR The PFODR register stores the output data for the pins that are used as the general output port. PF6ODR PF5ODR PF4ODR...
Page 277: Pin Functions
Section 8 I/O Ports 8.15.4 Pin Functions • PF7/ExPW15, PF6/ExPW14 The function of port F pins is switched as shown below according to the combination of the PWMAS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the PFnDDR bit. PWMAS PFnDDR ...
Page 278 Section 8 I/O Ports • PF3/IRQ11/ExTMOX The pin function is switched as shown below according to the combination of the TMOXS bit in PTCNT0, OS3 to OS0 bits in TCSR of TMR_X, and PF3DDR bit. When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ11 input pin.
Page 279: Port F Nch-Od Control Register (Pfnocr)
Section 8 I/O Ports 8.15.5 Port F Nch-OD control register (PFNOCR) The individual bits of PFNOCR specify output driver type for the pins of port F that is specified to output. Bit Name Initial Value Description PF7NOCR 0: CMOS (P channel driver is enable) PF6NOCR 1: N channel open-drain PF5NOCR...
Page 280: Port F Input Pull-Up Mos
Section 8 I/O Ports 8.15.7 Port F Input Pull-Up MOS Port F has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.11 summarizes the input pull-up MOS states.
Page 281: Port G
Section 8 I/O Ports 8.16 Port G Port G is an 8-bit I/O port. Port G pins also function as the interrupt input pins, and TMR_0, TMR_1, TMR_X, TMR_Y input pins and IIC_0, and IIC_1 input/output pins. The output format for port G is NMOS push-pull output.
Page 282: Port G Output Data Register
Section 8 I/O Ports 8.16.2 Port G Output Data Register (PGODR) PGODR stores output data for the port G pins. Bit Name Initial Value Description PG7ODR The PGODR register stores the output data for the pins that are used as the general output port. PG6ODR PG5ODR PG4ODR...
Page 283: Noise Canceller Enable Register
Section 8 I/O Ports 8.16.4 Noise Canceller Enable Register (PGNCE) PGNCE enables or disables the noise cancel circuit at port G. To use the port G pins as the IIC_0 and IIC_1input/output pins, these bits in PGNCE should be disabled. Bit Name Initial Value Description...
Page 284: Noise Cancel Cycle Setting Register
Section 8 I/O Ports 8.16.6 Noise Cancel Cycle Setting Register (PGNCCS) PGNCCS controls the sampling cycles of the noise canceller. Bit Name Initial Value Description 7 to 3  Undefined Reserved The read data is undefined. The initial value should not be changed.
Page 285: Pin Functions
Section 8 I/O Ports 8.16.7 Pin Functions • PG7/ExIRQ15/ExSCLB The pin function is switched as shown below according to the combination of the SCL1BS and SCL0BS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG7DDR bit. When the ISS15 bit in ISSR16 is set to 1 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin.
Page 286 Section 8 I/O Ports • PG6/ExIRQ14/ExSDAB The pin function is switched as shown below according to the combination of the SDA1BS and SDA0BS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG6DDR bit. When the ISS14 bit in ISSR16 is set to 1 and the IRQ14E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ14 input pin.
Page 287 Section 8 I/O Ports • PG5/ExIRQ13/ExSCLA The pin function is switched as shown below according to the combination of the SCL1AS and SCL0AS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin.
Page 288 Section 8 I/O Ports • PG4/ExIRQ12/ExSDAA The pin function is switched as shown below according to the combination of the SDA1AS and SDA0AS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG4DDR bit. When the ISS12 bit in ISSR16 is set to 1 and the IRQ12E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ12 input pin.
Page 289 Section 8 I/O Ports • PG2/ExIRQ10/ExTMIX The pin function is switched as shown below according to the PG2DDR bit. When the TMIXS bit in PTCNT0 and the CCLR1 and CCLR0 bits in TCR of TMR_X are cleared to 0, this pin is used as the ExTMIX (ExTMRIX) input pin.
Page 290: Port G Nch-Od Control Register
Section 8 I/O Ports 8.16.8 Port G Nch-OD control register (PGNOCR) The individual bits of PGNOCR specify output driver type for the pins of port G that is specified to output. Bit Name Initial Value Description PG7NOCR 0: NMOS push-pull (N channel driver in V side is enable) PG6NOCR...
Page 291: Change Of Peripheral Function Pins
Section 8 I/O Ports 8.17 Change of Peripheral Function Pins For the 8-bit timer input/output, 8-bit PWM timer output, and IIC input/output, the multi-function I/O ports can be changed. I/O ports that also function as the external sub-clock input pin, 8-bit timer input/output pins, and the 8-bit PWM timer output pins are changed according to the setting of PTCNT0.
Page 292: Port Control Register 1 (Ptcnt1)
Section 8 I/O Ports 8.17.2 Port Control Register 1 (PTCNT1) PTCNT1 selects ports that also function as IIC input/output pins. Bit Name Initial Value R/W Description SCL0AS IIC0 IIC1 SCL1AS 0000: P52/SCL0 P86/SCL1 SCL0BS 1000: PG5/ExSCLA P86/SCL1 SCL1BS 0100: P52/SCL0 PG5/ExSCLA 0010: PG7/ExSCLB...
Page 293: Port Control Register 2 (Ptcnt2)
Section 8 I/O Ports 8.17.3 Port Control Register 2 (PTCNT2) PTCNT2 selects ports that also function as docking LPC input/output pins. Setting 1 to one of LPC3E to LPC1E in HICR0 and LPC4E in HICR4 enables this function. Bit Name Initial Value Description LPCS...
Page 294 Section 8 I/O Ports Rev. 3.00 Jul. 14, 2005 Page 246 of 986 REJ09B0098-0300...
Page 295: Section 9 8-Bit Pwm Timer (Pwm)
Section 9 8-Bit PWM Timer (PWM) Section 9 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with eight outputs. Eight output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division.
Page 296: Figure 9.1 Block Diagram Of Pwm Timer
Section 9 8-Bit PWM Timer (PWM) Figure 9.1 shows a block diagram of the PWM timer. P20/PW8 P21/PW9 P22/PW10 Comparator 8 PWDR8 Module data bus P23/PW11 Comparator 9 PWDR9 P24/PW12 Comparator 10 PWDR10 Internal PF4/ExPW12 data bus Comparator 11 PWDR11 P25/PW13 Comparator 12 PWDR12...
Page 297: Input/Output Pins
Section 9 8-Bit PWM Timer (PWM) Input/Output Pins Table 9.1 shows the PWM output pins. Table 9.1 Pin Configuration Name Abbreviation Function PWM output 15 to 8 PW15 to PW8 Output PWM timer pulse output 15 to 8 ExPWM output 15 to 12 ExPW15 to ExPW12 A pin for outputting is selected among PWn and ExPWn.
Page 298: Pwm Register Select (Pwsl)
Section 9 8-Bit PWM Timer (PWM) 9.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Name Initial Value Description PWCKE PWM Clock Enable PWCKS PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM.
Page 299: Pwm Data Registers 15 To 8 (Pwdr15 To Pwdr8)
Section 9 8-Bit PWM Timer (PWM) Table 9.2 Internal Clock Selection PWSL PCSR PWCKE PWCKS PWCKB PWCKA Description — — — Clock input is disabled (Initial value) φ (system clock) is selected — — φ/2 is selected φ/4 is selected φ/8 is selected φ/16 is selected Resolution, PWM Conversion Period, and Carrier Frequency when φ...
Page 300: Pwm Data Polarity Register B (Pwdprb)
Section 9 8-Bit PWM Timer (PWM) 9.3.3 PWM Data Polarity Register B (PWDPRB) PWDPR selects the PWM output phase. • PWDPRB Bit Name Initial Value Description OS15 Output Select 15 to 8 OS14 These bits select the PWM output phase. Bits OS15 to OS13 OS8 correspond to outputs PW15 to PW8.
Page 301: Peripheral Clock Select Register (Pcsr)
Section 9 8-Bit PWM Timer (PWM) To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output. DR data is output when the corresponding pin is used as port output. A value corresponding to PWM 256/256 output is determined by the OS bit, so the value should have been set to DR beforehand.
Page 302: Operation
Section 9 8-Bit PWM Timer (PWM) Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse. Table 9.4 Duty Cycle of Basic Pulse Upper 4 Bits...
Page 303: Figure 9.2 Example Of Additional Pulse Timing (When Upper 4 Bits Of Pwdr = B'1000)
Section 9 8-Bit PWM Timer (PWM) The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse.
Page 304: Pwm Setting Example
Section 9 8-Bit PWM Timer (PWM) 9.4.1 PWM Setting Example 1-conversion cycle PWDR Basic Additiona setting example Duty cycle waveform pulse H'7F 127/256 112 pulses 15 pulses H'80 128/256 128 pulses 0 pulses H'81 129/256 128 pulses 1 pulse H'82 130/256 128 pulses 2 pulses...
Page 305: Usage Notes
Section 9 8-Bit PWM Timer (PWM) Usage Notes 9.5.1 Module Stop Mode Setting PWM operation can be enabled or disabled by the module stop control register. In the initial state, PWM operation is disabled. Access to PWM registers is enabled when module stop mode is cancelled.
Page 306 Section 9 8-Bit PWM Timer (PWM) Rev. 3.00 Jul. 14, 2005 Page 258 of 986 REJ09B0098-0300...
Page 307: Section 10 14-Bit Pwm Timer (Pwmx)
Section 10 14-Bit PWM Timer (PWMX) Section 10 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 10.1 Features •...
Page 308: Input/Output Pins
Section 10 14-Bit PWM Timer (PWMX) 10.2 Input/Output Pins Table 10.1 lists the PWMX (D/A) module input and output pins. Table 10.1 Pin Configuration Name Abbreviation I/O Function PWMX output pin 0 PWX0 Output PWMX output of channel A PWMX output pin 1 PWX1 Output PWMX output of channel B...
Page 309: Pwmx (D/A) Counter (Dacnt)
Section 10 14-Bit PWM Timer (PWMX) 10.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits.
Page 310: Pwmx (D/A) Data Registers A And B (Dadra And Dadrb)
Section 10 14-Bit PWM Timer (PWMX) 10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP).
Page 311 Section 10 14-Bit PWM Timer (PWMX) • DADRB Bit Name Initial Value Description DA13 D/A Data 13 to 0 DA12 These bits set a digital value to be converted to an analog value. DA11 In each base cycle, the DACNT value is continually DA10 compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to...
Page 312: Pwmx (D/A) Control Register (Dacr)
Section 10 14-Bit PWM Timer (PWMX) 10.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit Name Initial Value Description  R/W` Reserved The initial value should not be changed. PWME PWMX Enable Starts or stops the PWM D/A counter (DACNT).
Page 313: Peripheral Clock Select Register (Pcsr)
Section 10 14-Bit PWM Timer (PWMX) 10.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Bit Name Initial Value Description  Reserved  The initial value should not be changed. PWCKXB PWMX clock select PWCKXA These bits select a clock cycle with the CKS bit of DACR of PWMX being 1.
Page 314: Bus Master Interface
Section 10 14-Bit PWM Timer (PWMX) 10.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP).
Page 315: Figure 10.2 (1) Dacnt Access Operation (1) [Cpu → Dacnt(H'aa57) Writing]
Section 10 14-Bit PWM Timer (PWMX) Table 10.3 Reading/Writing to 16-bit Registers Read Write Register Word Byte Word Byte × DADRA, DADRB × × DACNT [Legend] Enabled access. Word-unit access includes accessing byte sequentially, first upper byte, and then lower byte.
Page 316: Figure 10.2 (2) Dacnt Access Operation (2) [Dacnt → Cpu(H'aa57) Reading]
Section 10 14-Bit PWM Timer (PWMX) (a) Read upper byte Module data bus [H'AA] Bus interface Upper byte TEMP [H'AA] DACNTH DACNTL (b) Read lower byte Module data bus [H'57] Bus interface Lower byte TEMP [H'AA] DACNTH DACNTL [H'AA] [H'57] Figure 10.2 (2) DACNT Access Operation (2) [DACNT →...
Page 317: Operation
Section 10 14-Bit PWM Timer (PWMX) 10.5 Operation A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. DA13 to DA0 in DADR corresponds to the total width (T ) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1).
Page 318: Table 10.4 Settings And Operation (Examples When Φ = 20 Mhz)
Section 10 14-Bit PWM Timer (PWMX) Table 10.4 Settings and Operation (Examples when φ = 20 MHz) PCSR Fixed DADR Bits Reso- PWCKX0 lution Conver- PWCKX1 Bit Data Conversion Accuracy Base sion TL/TH (Bits) (µs) Cycle Cycle (OS = 0/OS = 1) Cycle* ...
Page 319 Section 10 14-Bit PWM Timer (PWMX) PCSR Fixed DADR Bits Reso- PWCKX0 Bit Data lution Conver- Conversion PWCKX1 Accuracy Base sion TL/TH Cycle* (Bits) (µs) Cycle Cycle (OS = 0/OS = 1) 12.8 819.2 209.7 Always low/high output 209.7 ms DA13 to 0 = H'0000 to H'00FF (µs) (ms)
Page 320: Figure 10.4 Output Waveform (Os = 0, Dadr Corresponds To T L )
Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle f255 f256 L255 L256 = ··· = t = T× 64 f255 f256 + ··· + t L255 L256 a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle = ···...
Page 321: Figure 10.5 Output Waveform (Os = 1, Dadr Corresponds To T H )
Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle f255 f256 H255 H256 = ··· = t = T× 64 f255 f256 + ··· + t H255 H256 a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle = ···...
Page 322: Figure 10.7 Output Waveform When Dadr = H'0207 (Os = 1)
Section 10 14-Bit PWM Timer (PWMX) Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 10.5. Thus, an additional pulse of 1/256 × (T) is to be added to the base pulse.
Page 323: Table 10.5 Locations Of Additional Pulses Added To Base Pulse (When Cfs = 1)
Section 10 14-Bit PWM Timer (PWMX) Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) Rev. 3.00 Jul. 14, 2005 Page 275 of 986 REJ09B0098-0300...
Page 324: Usage Notes
Section 10 14-Bit PWM Timer (PWMX) 10.6 Usage Notes 10.6.1 Module Stop Mode Setting PWMX operation can be enabled or disabled by using the module stop control register. In the initial state, PWMX operation is disabled. Register access is enabled by clearing module stop mode.
Page 325: Section 11 16-Bit Free-Running Timer (Frt)
Section 11 16-Bit Free-Running Timer (FRT) Section 11 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16- bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods.
Page 326: Figure 11.1 Block Diagram Of 16-Bit Free-Running Timer
Section 11 16-Bit Free-Running Timer (FRT) External clock Internal clock OCRAR/F φ/2 φ/8 φ/32 FTCI Clock Clock selector OCRA Compare-match A Comparator A FTOA Internal data bus Overflow FTOB Clear FTIA Compare-match B Comparator B Control logic FTIB FTIC OCRB FTID Input capture ICRA...
Page 327: Input/Output Pins
Section 11 16-Bit Free-Running Timer (FRT) 11.2 Input/Output Pins Table 11.1 lists the FRT input and output pins. Table 11.1 Pin Configuration Name Abbreviation Function Counter clock input pin FTCI Input FRC counter clock input Output compare A output pin FTOA Output Output compare A output...
Page 328: Free-Running Counter (Frc)
Section 11 16-Bit Free-Running Timer (FRT) 11.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1.
Page 329: Output Compare Registers Ar And Af (Ocrar And Ocraf)
Section 11 16-Bit Free-Running Timer (FRT) ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000. 11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF.
Page 330: Timer Interrupt Enable Register (Tier)
Section 11 16-Bit Free-Running Timer (FRT) 11.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Name Initial Value Description ICIAE Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Page 331: Timer Control/Status Register (Tcsr)
Section 11 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description OCIBE Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled OVIE Timer Overflow Interrupt Enable...
Page 332 Section 11 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description ICFB R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB.
Page 333 Section 11 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description OCFA R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA OCFB R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches...
Page 334: Timer Control Register (Tcr)
Section 11 16-Bit Free-Running Timer (FRT) 11.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Name Initial Value Description IEDGA Input Edge Select A Selects the rising or falling edge of the input capture A...
Page 335: Timer Output Compare Control Register (Tocr)
Section 11 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description CKS1 Clock Select 1, 0 CKS0 Select clock source for FRC. 00: φ/2 internal clock source 01: φ/8 internal clock source 10: φ/32 internal clock source 11: External clock source (counting at FTCI rising edge) 11.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access...
Page 336 Section 11 16-Bit Free-Running Timer (FRT) Bit Name Initial Value Description OCRS Output Compare Register Select OCRA and OCRB share the same address. The OCRS determines which register is selected when the shared address is read from or written to. The operation of OCRA or OCRB is not affected.
Page 337: Operation
Section 11 16-Bit Free-Running Timer (FRT) 11.4 Operation 11.4.1 Pulse Output Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software.
Page 338: Operation Timing
Section 11 16-Bit Free-Running Timer (FRT) 11.5 Operation Timing 11.5.1 FRC Increment Timing Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ).
Page 339: Output Compare Output Timing
Section 11 16-Bit Free-Running Timer (FRT) 11.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare output pin (FTOA or FTOB).
Page 340: Input Capture Input Timing
Section 11 16-Bit Free-Running Timer (FRT) 11.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected.
Page 341: Buffered Input Capture Input Timing
Section 11 16-Bit Free-Running Timer (FRT) 11.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Page 342: Timing Of Input Capture Flag (Icf) Setting
Section 11 16-Bit Free-Running Timer (FRT) CPU read cycle of ICRA or ICRC φ FTIA Input capture signal Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) 11.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA to ICRD).
Page 343: Timing Of Output Compare Flag (Ocf) Setting
Section 11 16-Bit Free-Running Timer (FRT) 11.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value.
Page 344: Automatic Addition Timing
Section 11 16-Bit Free-Running Timer (FRT) φ H'FFFF H'0000 Overflow signal Figure 11.13 Timing of Overflow Flag (OVF) Setting 11.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed.
Page 345: 11.5.10 Mask Signal Generation Timing
Section 11 16-Bit Free-Running Timer (FRT) 11.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal.
Page 346: Interrupt Sources
Section 11 16-Bit Free-Running Timer (FRT) 11.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt.
Page 347: Usage Notes
Section 11 16-Bit Free-Running Timer (FRT) 11.7 Usage Notes 11.7.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict.
Page 348: Conflict Between Frc Write And Increment
Section 11 16-Bit Free-Running Timer (FRT) 11.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict. Write cycle of FRC φ...
Page 349: Conflict Between Ocr Write And Compare-Match
Section 11 16-Bit Free-Running Timer (FRT) 11.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of conflict.
Page 350: Switching Of Internal Clock And Frc Operation
Section 11 16-Bit Free-Running Timer (FRT) φ OCRAR (OCRAF) Address address Internal write signal Old data New data OCRAR (OCRAF) Disabled Compare-match signal Automatic addition is not performed because compare-match signals are disabled. Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) 11.7.4 Switching of Internal Clock and FRC Operation...
Page 351: Table 11.3 Switching Of Internal Clock And Frc Operation
Section 11 16-Bit Free-Running Timer (FRT) Table 11.3 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from Clock before switchover low to low Clock after switchover FRC clock N + 1 CKS bit rewrite Switching from...
Page 352: Module Stop Mode Setting
Section 11 16-Bit Free-Running Timer (FRT) Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from Clock before switchover high to high Clock after switchover FRC clock N + 1 N + 2 CKS bit rewrite Note: Generated on the assumption that the switchover is a falling edge;...
Page 353: Section 12 16-Bit Timer Pulse Unit (Tpu)
Section 12 16-Bit Timer Pulse Unit (TPU) Section 12 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 12.1 and figure 12.1, respectively.
Page 354: Figure 12.1 Block Diagram Of Tpu
Section 12 16-Bit Timer Pulse Unit (TPU) Clock input φ/1 Internal clock: φ/4 φ/16 φ/64 Internal data bus φ/256 φ/1024 A/D converter convertion start signal External clock: TCLKA TCLKB TCLKC TCLKD Input/output pins Interrupt request signals Channel 0: TGI0A Channel 0: TIOCA0 TGI0B TIOCB0...
Page 355: Table 12.1 Tpu Functions
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.1 TPU Functions Item Channel 0 Channel 1 Channel 2 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/64 φ/64 φ/64 φ/256 φ/1024 TCLKA TCLKB TCLKA TCLKA TCLKC TCLKB TCLKB TCLKD TCLKC...
Page 356 Section 12 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 DTC activation TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture A/D converter trigger TGRA_0 compare TGRA_1 compare TGRA_2 compare match or input capture match or input capture...
Page 357: Input/Output Pins
Section 12 16-Bit Timer Pulse Unit (TPU) 12.2 Input/Output Pins Table 12.2 Pin Configuration Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 358: Register Descriptions
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3 Register Descriptions The TPU has the following registers. • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) •...
Page 359: Timer Control Register (Tcr)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only when TCNT operation is stopped.
Page 360: Table 12.3 Cclr2 To Cclr0 (Channel 0)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.3 CCLR2 to CCLR0 (channel 0) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing...
Page 361: Table 12.5 Tpsc2 To Tpsc0 (Channel 0)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.5 TPSC2 to TPSC0 (channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 362: Table 12.7 Tpsc2 To Tpsc0 (Channel 2)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.7 TPSC2 to TPSC0 (channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 363: Timer Mode Register (Tmdr)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped.
Page 364: Table 12.8 Md3 To Md0
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.8 MD3 to MD0 Bit 3 Bit2 Bit 1 Bit 0 Description MD3* MD2* Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 365: Timer I/O Control Register (Tior)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting.
Page 366: Table 12.9 Tiorh_0 (Channel 0)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.9 TIORH_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 367: Table 12.10 Tiorh_0 (Channel 0)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.10 TIORH_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 368: Table 12.11 Tiorl_0 (Channel 0)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.11 TIORL_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRA_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled Compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 369: Table 12.12 Tiorl_0 (Channel 0)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.12 TIORL_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 1 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 370: Table 12.13 Tior_1 (Channel 1)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.13 TIOR_1 (channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 371: Table 12.14 Tior_1 (Channel 1)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.14 TIOR_1 (channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 372: Table 12.15 Tior_2 (Channel 2)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.15 TIOR_2 (channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 373: Table 12.16 Tior_2 (Channel 2)
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.16 TIOR_2 (channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 374: Timer Interrupt Enable Register (Tier)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit Name Initial value Description TTGE A/D Conversion Start Request Enable...
Page 375 Section 12 16-Bit Timer Pulse Unit (TPU) Bit Name Initial value Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 376: Timer Status Register (Tsr)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Bit Name Initial value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channel 1 and 2.
Page 377 Section 12 16-Bit Timer Pulse Unit (TPU) Bit Name Initial value Description TGFD R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Page 378 Section 12 16-Bit Timer Pulse Unit (TPU) Bit Name Initial value Description TGFB R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register •...
Page 379: Timer Counter (Tcnt)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units;...
Page 380: Timer Synchro Register (Tsyr)
Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to Bit Name Initial Value R/W Description...
Page 381: Interface To Bus Master
Section 12 16-Bit Timer Pulse Unit (TPU) 12.4 Interface to Bus Master 12.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units;...
Page 382: Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ Tcr (Upper 8 Bits)]
Section 12 16-Bit Timer Pulse Unit (TPU) Internal data bus Module master Bus interface data bus Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus TMDR Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus Module master...
Page 383: Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 12.5 Operation 12.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of free- running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Page 384: Figure 12.7 Free-Running Counter Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter.
Page 385: Figure 12.8 Periodic Counter Operation
Section 12 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 12.8 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 386: Figure 12.10 Example Of 0 Output/1 Output Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 12.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B.
Page 387: Figure 12.12 Example Of Input Capture Operation Setting Procedure
Section 12 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. 1.
Page 388: Figure 12.13 Example Of Input Capture Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 12.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 389: Synchronous Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 390: Figure 12.15 Example Of Synchronous Operation
Section 12 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 12.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 391: Buffer Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 392: Figure 12.18 Example Of Buffer Operation Setting Procedure
Section 12 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure Figure 12.18 shows an example of the buffer operation setting procedure. Buffer operation Designate TGR as an input capture register or output compare register by means of TIOR. Designate TGR for buffer operation with bits BFA and BFB in TMDR.
Page 393: Figure 12.19 Example Of Buffer Operation (1)
Section 12 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation 1. When TGR is an output compare register Figure 12.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 394: Figure 12.20 Example Of Buffer Operation (2)
Section 12 16-Bit Timer Pulse Unit (TPU) 2. When TGR is an input capture register Figure 12.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 395: Pwm Modes
Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty.
Page 396: Figure 12.21 Example Of Pwm Mode Setting Procedure
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.18 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0 TGRA_1 TIOCA1 TIOCA1 TGRB_1 TIOCB1 TGRA_2 TIOCA2 TIOCA2...
Page 397: Figure 12.22 Example Of Pwm Mode Operation (1)
Section 12 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation Figure 12.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value.
Page 398: Figure 12.23 Example Of Pwm Mode Operation (2)
Section 12 16-Bit Timer Pulse Unit (TPU) Figure 12.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 399: Figure 12.24 Example Of Pwm Mode Operation (3)
Section 12 16-Bit Timer Pulse Unit (TPU) Figure 12.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 400: Phase Counting Mode
Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 401: Figure 12.26 Example Of Phase Counting Mode 1 Operation
Section 12 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1.
Page 402: Figure 12.27 Example Of Phase Counting Mode 2 Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 12.27 shows an example of phase counting mode 2 operation, and table 12.21 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count...
Page 403: Figure 12.28 Example Of Phase Counting Mode 3 Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 12.28 shows an example of phase counting mode 3 operation, and table 12.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 404: Figure 12.29 Example Of Phase Counting Mode 4 Operation
Section 12 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 12.29 shows an example of phase counting mode 4 operation, and table 12.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 405: Interrupts
Section 12 16-Bit Timer Pulse Unit (TPU) 12.6 Interrupts 12.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually.
Page 406: Table 12.24 Tpu Interrupts
Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.24 TPU Interrupts Channel Name Interrupt Source Interrupt Flag DTC Activation Priority TGI0A TGRA_0 input TGFA Enable High capture/compare match TGI0B TGRB_0 input TGFB Enable capture/compare match TGI0C TGRC_0 input TGFC Enable capture/compare match TGI0D TGRD_0 input...
Page 407: Dtc Activation
Section 12 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
Page 408: Operation Timing
Section 12 16-Bit Timer Pulse Unit (TPU) 12.7 Operation Timing 12.7.1 Input/Output Timing TCNT Count Timing Figure 12.30 shows TCNT count timing in internal clock operation, and figure 12.31 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT...
Page 409: Figure 12.32 Output Compare Output Timing
Section 12 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 410: Figure 12.34 Counter Clear Timing (Compare Match)
Section 12 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 12.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 12.35 shows the timing when counter clearing by input capture occurrence is specified. φ...
Page 411: Figure 12.36 Buffer Operation Timing (Compare Match)
Section 12 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 12.36 and 12.37 show the timing in buffer operation. φ TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 12.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT TGRA, TGRB...
Page 412: Interrupt Signal Timing
Section 12 16-Bit Timer Pulse Unit (TPU) 12.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 12.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ...
Page 413: Figure 12.39 Tgi Interrupt Timing (Input Capture)
Section 12 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture Figure 12.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal TCNT...
Page 414: Figure 12.40 Tciv Interrupt Setting Timing
Section 12 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 12.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 12.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 415: Figure 12.42 Timing For Status Flag Clearing By Cpu
Section 12 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 12.42 shows the timing for status flag clearing by the CPU, and figure 12.43 shows the timing for status flag clearing by the DTC.
Page 416: Usage Notes
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8 Usage Notes 12.8.1 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 417: Conflict Between Tcnt Write And Clear Operations
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.3 Conflict between TCNT Write and Clear Operations If the counter clear signal is generated in the T state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 12.45 shows the timing in this case. TCNT write cycle φ...
Page 418: Conflict Between Tgr Write And Compare Match
Section 12 16-Bit Timer Pulse Unit (TPU) TCNT write cycle φ TCNT address Address Write signal TCNT input clock TCNT TCNT write data Figure 12.46 Conflict between TCNT Write and Increment Operations 12.8.5 Conflict between TGR Write and Compare Match If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited.
Page 419: Conflict Between Buffer Register Write And Compare Match
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.6 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 12.48 shows the timing in this case. TGR write cycle φ...
Page 420: Conflict Between Tgr Read And Input Capture
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.7 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 12.49 shows the timing in this case. TGR read cycle φ...
Page 421: Conflict Between Tgr Write And Input Capture
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.8 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 12.50 shows the timing in this case.
Page 422: Conflict Between Buffer Register Write And Input Capture
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.9 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 12.51 shows the timing in this case.
Page 423: 12.8.10 Conflict Between Overflow/Underflow And Counter Clearing
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.10 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 424: 12.8.11 Conflict Between Tcnt Write And Overflow/Underflow
Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.11 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Page 425: Section 13 8-Bit Timer (Tmr)
Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 426 Section 13 8-Bit Timer (TMR) • Selection of general ports for timer input/output  TMCI0/ExTMCI0, TMCI1/ExTMCI1, or TMIX/ExTMIX  TMIY/ExTMIY or TMOX/ExTMOX Figures 13.1 and 13.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X. Rev.
Page 427 Section 13 8-Bit Timer (TMR) External clock Internal clock sources sources TMR_0 TMCI0/ExTMCI1 φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024 TMCI1/ExTMCI0 TMR_1 φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048 Clock 1 Clock 0 Clock select TCORA_0 TCORA_1 Compare-match A1 Compare-match A0 Comparator A_0 Comparator A_1 Overflow 1 TMO0...
Page 428: Figure 13.2 Block Diagram Of 8-Bit Timer (Tmr_Y And Tmr_X)
Section 13 8-Bit Timer (TMR) External clock Internal clock sources sources TMR_X TMCIY /ExTMCIX φ, φ φ φ φ φ TMCIX /ExTMCIY /2048, /4096, /8192 TMR_Y φ φ φ φ φ φ /256, /2048, /4096, /8192, /16384 Clock X Clock Y Clock select TCORA_Y...
Page 429: Input/Output Pins
Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration Channel Name Symbol Function TMR_0 Timer output TMO0 Output Output controlled by compare-match Timer clock input TMCI0, Input External clock input for the counter ExTMCI0...
Page 430: Register Descriptions
Section 13 8-Bit Timer (TMR) 13.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). TMR_0 • Timer counter_0 (TCNT_0) • Time constant register A_0 (TCORA_0) •...
Page 431: Timer Counter (Tcnt)
Section 13 8-Bit Timer (TMR) • Input capture register F (TICRF) • Timer connection register I (TCONRI) For both TMR_Y and TMR_X • Timer XY control register (TCRXY) Note: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be switched by the TMRX/Y bit in TCONRS.
Page 432: Time Constant Register B (Tcorb)
Section 13 8-Bit Timer (TMR) 13.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_X and TCORB_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1.
Page 433 Section 13 8-Bit Timer (TMR) Bit Name Initial Value R/W Description CCLR1 Counter Clear 1, 0 CCLR0 These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input CKS2 Clock Select 2 to 0...
Page 434: Table 13.2 Clock Input To Tcnt And Count Condition (1)
Section 13 8-Bit Timer (TMR) Table 13.2 Clock Input to TCNT and Count Condition (1) STCR Channel CKS2 Description CKS1 CKS0 ICKS1 ICKS0 TMR_0 — — Disables clock input — Increments at falling edge of internal clock φ/8 — Increments at falling edge of internal clock φ/2 —...
Page 435: Table 13.2 Clock Input To Tcnt And Count Condition (2)
Section 13 8-Bit Timer (TMR) STCR Channel CKS2 Description CKS1 CKS0 ICKS1 ICKS0 Common 1 — — Increments at rising edge of external clock — — Increments at falling edge of external clock — — Increments at both rising and falling edges of external clock Note: If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock...
Page 436 Section 13 8-Bit Timer (TMR) TCRXY Channel CKS2 Description CKS1 CKS0 CKSX CKSY TMR_X — Disables clock input Increments at φ — Increments at φ/2 — Increments at φ/4 — — Disables clock input — Disables clock input Increments at φ/2048 —...
Page 437: Timer Control/Status Register (Tcsr)
Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. • TCSR_0 Bit Name Initial Value R/W Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA...
Page 438 Section 13 8-Bit Timer (TMR) Bit Name Initial Value R/W Description Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 439 Section 13 8-Bit Timer (TMR) Bit Name Initial Value R/W Description Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Output Select 1, 0...
Page 440 Section 13 8-Bit Timer (TMR) Bit Name Initial Value R/W Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order.
Page 441 Section 13 8-Bit Timer (TMR) • TCSR_Y Bit Name Initial Value R/W Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA R/(W)* Compare-Match Flag A [Setting condition]...
Page 442: Time Constant Register C (Tcorc)
Section 13 8-Bit Timer (TMR) Bit Name Initial Value R/W Description Output Select 1, 0 These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 443: Timer Input Select Register (Tisr)
Section 13 8-Bit Timer (TMR) 13.3.8 Timer Input Select Register (TISR) TISR permits or prohibits a signal source of external clock/reset input for the counter. Bit Name Initial Value R/W Description 7 to 1 — All 1 R/(W) Reserved The initial value should not be changed. Input Select Selects a timer clock/reset input pin (TMIY) as the signal source of external clock/reset input for the TMR_Y...
Page 444: Timer Connection Register S (Tconrs)
Section 13 8-Bit Timer (TMR) 13.3.10 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Bit Name Initial Value Description TMRX/Y TMR_X/TMR_Y Access Select For details, see table 13.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5...
Page 445: Operation
Section 13 8-Bit Timer (TMR) 13.4 Operation 13.4.1 Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA.
Page 446: Operation Timing
Section 13 8-Bit Timer (TMR) 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges.
Page 447: Timing Of Cmfa And Cmfb Setting At Compare-Match
Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated.
Page 448: Timing Of Counter Clear At Compare-Match
Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match.
Page 449: Timing Of Overflow Flag (Ovf) Setting
Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00...
Page 450: Tmr_0 And Tmr_1 Cascaded Connection
Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available.
Page 451: Tmr_Y And Tmr_X Cascaded Connection
Section 13 8-Bit Timer (TMR) 13.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY.
Page 452: Input Capture Operation
Section 13 8-Bit Timer (TMR) 13.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF.
Page 453: Figure 13.12 Timing Of Input Capture Signal (Input Capture Signal Is Input During Ticrr And Ticrf Read)
Section 13 8-Bit Timer (TMR) TICRR, TICRF read cycle φ TMRIX Input capture signal Figure 13.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) Selection of Input Capture Signal Input TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI.
Page 454: Interrupt Sources
Section 13 8-Bit Timer (TMR) 13.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.5 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR.
Page 455: Usage Notes
Section 13 8-Bit Timer (TMR) 13.9 Usage Notes 13.9.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T state of a TCNT write cycle as shown in figure 13.13, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU φ...
Page 456: Conflict Between Tcnt Write And Count-Up
Section 13 8-Bit Timer (TMR) 13.9.2 Conflict between TCNT Write and Count-Up If a count-up occurs during the T state of a TCNT write cycle as shown in figure 13.14, the counter write takes priority and the counter is not incremented. TCNT write cycle by CPU φ...
Page 457: Conflict Between Tcor Write And Compare-Match
Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T state of a TCOR write cycle as shown in figure 13.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
Page 458: Conflict Between Compare-Matches A And B
Section 13 8-Bit Timer (TMR) 13.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the operation follows the output status that is defined for compare-match A or B, according to the priority of the timer output shown in table 13.6.
Page 459: Table 13.7 Switching Of Internal Clocks And Tcnt Operation
Section 13 8-Bit Timer (TMR) Table 13.7 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from low Clock before to low level* switchover Clock after switchover TCNT clock TCNT...
Page 460: Mode Setting With Cascaded Connection
Section 13 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from high Clock before to high level switchover Clock after switchover TCNT clock TCNT N + 1 N + 2 CKS bit rewrite Notes: 1.
Page 461: Section 14 Watchdog Timer (Wdt)
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal.
Page 462: Figure 14.1 Block Diagram Of Wdt
Section 14 Watchdog Timer (WDT) φ/2 φ/64 WOVI0 φ/128 Interrupt (Interrupt request signal) φ/512 control Clock Overflow Clock φ/2048 selection Internal NMI φ/8192 Reset (Interrupt request signal* φ/32768 control φ/131072 RESO signal* Internal clock Internal reset signal* TCNT_0 TCSR_0 Module bus interface WDT_0 φ/2...
Page 463: Input/Output Pins
Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name Symbol Function RESO Reset output pin Output Outputs the counter overflow signal in watchdog timer mode External sub-clock input EXCL Input Inputs the clock pulses to the WDT_1...
Page 464: Timer Control/Status Register (Tcsr)
Section 14 Watchdog Timer (WDT) 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit Name Initial Value R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00).
Page 465 Section 14 Watchdog Timer (WDT) Bit Name Initial Value R/W Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz is enclosed in CKS0 parentheses. 000: φ/2 (frequency: 25.6 µs) 001: φ/64 (frequency: 819.2 µs) 010: φ/128 (frequency: 1.6 ms)
Page 466 Section 14 Watchdog Timer (WDT) • TCSR_1 Bit Name Initial Value R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Page 467 Section 14 Watchdog Timer (WDT) Bit Name Initial Value R/W Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow cycle for φ = 20 MHz and φSUB = 32.768 kHz is CKS0 enclosed in parentheses.
Page 468: Operation
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated.
Page 469: Interval Timer Mode
Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 OVF = 1* WT/IT = 1 Write H'00 to WT/IT = 1 Write H'00 to TME = 1 TCNT TME = 1 TCNT Internal reset signal 518 System clocks WT/IT : Timer mode select bit : Timer enable bit...
Page 470: Reso Signal Output Timing
Section 14 Watchdog Timer (WDT) φ TCNT H'FF H'00 Overflow signal (internal signal) Figure 14.4 OVF Flag Set Timing RESO Signal Output Timing 14.4.3 When TCNT overflows in watchdog timer mode, the OVF flag in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI.
Page 471: Interrupt Sources
Section 14 Watchdog Timer (WDT) 14.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine.
Page 472: Usage Notes
Section 14 Watchdog Timer (WDT) 14.6 Usage Notes 14.6.1 Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below.
Page 473: Conflict Between Timer Counter (Tcnt) Write And Increment
Section 14 Watchdog Timer (WDT) Reading from TCNT and TCSR (Example of WDT_0) These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the timer counter is not incremented.
Page 474: Changing Values Of Cks2 To Cks0 Bits
Section 14 Watchdog Timer (WDT) 14.6.3 Changing Values of CKS2 to CKS0 Bits If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits.
Page 475: Section 15 Serial Communication Interface (Sci, Irda)
Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 476 Section 15 Serial Communication Interface (SCI, IrDA) Asynchronous Mode: • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even, odd, or none • Receive error detection: Parity, overrun, and framing errors • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error •...
Page 477: Figure 15.1 Block Diagram Of Sci
Section 15 Serial Communication Interface (SCI, IrDA) Module data bus SCMR φ Baud rate φ/4 RxD1 generator φ/16 Transmission/ φ/64 reception control TxD1 Parity generation Clock Parity check External clock SCK1 [Legend] RSR: Receive shift register SCR: Serial control register RDR: Receive data register SSR: Serial status register TSR: Transmit shift register...
Page 478: Input/Output Pins
Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration Channel Symbol* Input/Output Function SCK1 Input/Output Channel 1 clock input/output RxD1/IrRxD Input Channel 1 receive data input (normal/IrDA) TxD1/IrTxD Output Channel 1 transmit data output (normal/IrDA)
Page 479: Register Descriptions
Section 15 Serial Communication Interface (SCI, IrDA) 15.3 Register Descriptions The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode;...
Page 480: Transmit Data Register (Tdr)
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission.
Page 481 Section 15 Serial Communication Interface (SCI, IrDA) • Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0) Bit Name Initial Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length.
Page 482 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 Clock Select 1,0 CKS0...
Page 483 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 15.7.2, Data Format (Except in Block Transfer Mode).
Page 484: Serial Control Register (Scr)
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 15.9, Interrupt Sources.
Page 485 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description CKE1 Clock Enable 1, 0 CKE0 These bits select the clock source and SCK pin function. • Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency...
Page 486 Section 15 Serial Communication Interface (SCI, IrDA) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled.
Page 487: Serial Status Register (Ssr)
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Page 488 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description ORER R/(W)* Overrun Error [Setting condition] • When the next serial reception is completed while RDRF = 1 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 R/(W)* Framing Error...
Page 489 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. MPBT Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame.
Page 490 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description RDRF R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] •...
Page 491 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description TEND Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR. [Setting conditions] •...
Page 492: Smart Card Mode Register (Scmr)
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Name Initial Value Description  7 to 4 All 1 Reserved These bits are always read as 1 and cannot be modified.
Page 493: Bit Rate Register (Brr)
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode.
Page 494: Table 15.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate settable for each frequency. Table 15.6 and 15.8 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
Page 495 Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 7.3728 9.8304 Bit Rate Error Error Error Error (bit/s) –0.07 0.03 –0.26 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16 2400 0.00...
Page 496: Table 15.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 12.288 14.7456 Bit Rate Error Error Error Error (bit/s) 0.03 0.08 –0.17 0.70 0.16 0.00 0.16 0.00 0.16 0.00...
Page 497 Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 17.2032 19.6608 Bit Rate Error Error Error Error Error (bit/s) 0.03 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 207 0.16 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16...
Page 498: Table 15.4 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate Maximum Bit φ (MHz) φ (MHz) (bit/s) Rate (bit/s) 125000 375000 44.9152 153600 12.288 384000 156250 437500 187500 14.7456 460800 6.144 192000 500000...
Page 499: Table 15.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Rate (bit/s) n             2.5k 100k 250k 500k 1∗...
Page 500: Table 15.7 Maximum Bit Rate With External Clock Input (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) External Input Maximum Bit External Input Maximum Bit φ (MHz) φ (MHz) Clock (MHz) Rate (bit/s) Clock (MHz) Rate (bit/s) 0.6667 666666.7 2.3333 2333333.3...
Page 501: Keyboard Comparator Control Register (Kbcomp)
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 Keyboard Comparator Control Register (KBCOMP) KBCOMP controls IrDA operation of SCI_1. Bit Name Initial Value Description IrDA Enable Specifies SCI_1 I/O pins for either normal SCI or IrDA. 0: TxD1/IrTxD and RxD1/IrRxD pins function as TxD1 and RxD1 pins, respectively 1: TxD1/IrTxD and RxD1/IrRxD pins function as IrTxD and IrRxD pins, respectively...
Page 502 Section 15 Serial Communication Interface (SCI, IrDA) Bit Name Initial Value Description IrRxINV IrRx Data Invert Specifies the inversion of the logic level of the input to IrRxD. When the inversion is specified, IrCKS2 to IrCKS0 specify the low-level width, not the high-level width.
Page 503: Operation In Asynchronous Mode
Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level).
Page 504: Table 15.10 Serial Transfer Formats (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transmit/Receive Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP...
Page 505: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 506: Clock
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
Page 507: Sci Initialization (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 508: Serial Data Transmission (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.5 Serial Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 509: Figure 15.7 Sample Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI, IrDA) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 510: Serial Data Reception (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 511: Table 15.11 Ssr Status Flags And Receive Data Handling
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Page 512: Figure 15.9 Sample Serial Reception Flowchart (1)
Section 15 Serial Communication Interface (SCI, IrDA) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 513: Figure 15.9 Sample Serial Reception Flowchart (2)
Section 15 Serial Communication Interface (SCI, IrDA) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 514: Multiprocessor Communication Function
Section 15 Serial Communication Interface (SCI, IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 515: Figure 15.10 Example Of Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle =...
Page 516: Multiprocessor Serial Data Transmission
Section 15 Serial Communication Interface (SCI, IrDA) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.
Page 517: Multiprocessor Serial Data Reception
Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 518: Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
Section 15 Serial Communication Interface (SCI, IrDA) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Set MPIE bit in SCR to 1 [3] SCI status check, ID reception and Read ORER and FER flags in SSR comparison:...
Page 519: Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)
Section 15 Serial Communication Interface (SCI, IrDA) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 520: Operation In Clocked Synchronous Mode
Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 521: Sci Initialization (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 522: Serial Data Transmission (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 523: Figure 15.16 Sample Sci Transmission Operation In Clocked Synchronous Mode
Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request request generated and TDRE flag cleared request generated...
Page 524: Figure 15.17 Sample Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI, IrDA) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Page 525: Serial Data Reception (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 526: Figure 15.19 Sample Serial Reception Flowchart
Section 15 Serial Communication Interface (SCI, IrDA) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 527: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 528: Figure 15.20 Sample Flowchart Of Simultaneous Serial Transmission And Reception
Section 15 Serial Communication Interface (SCI, IrDA) [1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data Start transmission/reception input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR [2] SCI status check and transmit data write:...
Page 529: Smart Card Interface Description
Section 15 Serial Communication Interface (SCI, IrDA) 15.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register.
Page 530: Figure 15.22 Data Formats In Normal Smart Card Interface Mode
Section 15 Serial Communication Interface (SCI, IrDA) In normal transmission/reception Output from the transmitting station When a parity error is generated Output from the transmitting station Output from the receiving station Legend Start bit D0 to D7 : Data bits Parity bit Error signal Figure 15.22 Data Formats in Normal Smart Card Interface Mode...
Page 531: Block Transfer Mode
Section 15 Serial Communication Interface (SCI, IrDA) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 15.24. Therefore, data in the start character in the figure is H'3F.
Page 532: Initialization
Section 15 Serial Communication Interface (SCI, IrDA) Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is determined by the formula below. M = (0.5 – 1/2 × 372) × 100 [%] = 49.866% 372 clock cycles 186 clock cycles...
Page 533: Serial Data Transmission (Except In Block Transfer Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval. Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, and initialize the SCI.
Page 534: Figure 15.26 Data Re-Transfer Operation In Sci Transmission Mode
Section 15 Serial Communication Interface (SCI, IrDA) (n + 1) th nth transfer frame Retransfer frame transfer frame (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR...
Page 535: Figure 15.28 Sample Transmission Flowchart
Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0 ? Error processing TEND = 1 ? Write data to TDR and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0 ? Error processing TEND = 1 ? Clear TE bit in SCR to 0...
Page 536: Serial Data Reception (Except In Block Transfer Mode)
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 15.29 shows the data re-transfer operation during reception. 1.
Page 537: Figure 15.30 Sample Reception Flowchart
Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start reception ORER = 0 and PER = 0? Error processing RDRF = 1 ? Read data from RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit in SCR to 0 Figure 15.30 Sample Reception Flowchart Rev.
Page 538: Clock Output Control
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0.
Page 539: Figure 15.32 Clock Stop And Restart Procedure
Section 15 Serial Communication Interface (SCI, IrDA) E. Make the transition to software standby mode. • At Transition from Software Standby Mode to Smart Card Interface Mode: 1. Cancel software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty ratio is then generated.
Page 540: Irda Operation
Section 15 Serial Communication Interface (SCI, IrDA) 15.8 IrDA Operation IrDA operation can be used with SCI_1. Figure 15.33 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 signals for SCI_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins).
Page 541: Figure 15.34 Irda Transmission And Reception
Section 15 Serial Communication Interface (SCI, IrDA) Transmission During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 15.34). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting).
Page 542 Section 15 Serial Communication Interface (SCI, IrDA) Reception During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI_1. Here, the input waveform can also be inverted using the IrRxINV bit in SCICR. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle.
Page 543: Table 15.12 Ircks2 To Ircks0 Bit Settings
Section 15 Serial Communication Interface (SCI, IrDA) High-Level Pulse Width Selection Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission.
Page 544: Interrupt Sources
Section 15 Serial Communication Interface (SCI, IrDA) 15.9 Interrupt Sources 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR.
Page 545: Interrupts In Smart Card Interface Mode
Section 15 Serial Communication Interface (SCI, IrDA) 15.9.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 15.14 SCI Interrupt Sources Channel Name Interrupt Source...
Page 546: Usage Notes
Section 15 Serial Communication Interface (SCI, IrDA) 15.10 Usage Notes 15.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 24, Power-Down Modes.
Page 547: 15.10.6 Restrictions On Using Dtc
Section 15 Serial Communication Interface (SCI, IrDA) 15.10.6 Restrictions on Using DTC When the external clock source is used as a synchronization clock, update TDR by the DTC and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 15.35).
Page 548: Figure 15.36 Sample Flowchart For Mode Transition During Transmission
Section 15 Serial Communication Interface (SCI, IrDA) TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC. Transmission [1] Data being transmitted is lost All data transmitted? halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing...
Page 549: Figure 15.37 Pin States During Transmission In Asynchronous Mode (Internal Clock)
Section 15 Serial Communication Interface (SCI, IrDA) Transition to Software standby software standby Transmission start Transmission end mode cancelled mode TE bit Port output pin input/output Port High output Start Stop Port input/output High output input/output output pin SCI TxD output Port Port TxD output...
Page 550: Figure 15.39 Sample Flowchart For Mode Transition During Reception
Section 15 Serial Communication Interface (SCI, IrDA) Reception Before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception.
Page 551: 15.10.8 Notes On Switching From Sck Pins To Port Pins
Section 15 Serial Communication Interface (SCI, IrDA) 15.10.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.40. Low pulse of half a cycle SCK/Port 1.
Page 552: Figure 15.41 Prevention Of Low Pulse Output At Switching From Sck Pins To Port Pins
Section 15 Serial Communication Interface (SCI, IrDA) High output SCK/Port 1. Transmission end Data Bit 6 Bit 7 2. TE = 0 4. C/A = 0 3. CKE1 = 1 5. CKE1 = 0 CKE1 CKE0 Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev.
Page 553: Section 16 I C Bus Interface (Iic)
Section 16 I C Bus Interface (IIC) Section 16 I C Bus Interface (IIC) This LSI has a two-channel I C bus interface. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 554 Section 16 I C Bus Interface (IIC) • Selection of 16 internal clocks (in master mode) • Direct bus drive (SCL/SDA pin)  Eight pins—P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB —(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Rev.
Page 555: Figure 16.1 Block Diagram Of I
Section 16 I C Bus Interface (IIC) Figure 16.1 shows a block diagram of the I C bus interface. Figure 16.2 shows an example of I/O pin connections to external circuits. Since I C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages.
Page 556: Figure 16.2 I C Bus Interface Connections (Example: This Lsi As Master)
Section 16 I C Bus Interface (IIC) (Master) This LSI (Slave 1) (Slave 2) Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) Rev. 3.00 Jul. 14, 2005 Page 508 of 986 REJ09B0098-0300...
Page 557: Input/Output Pins
Section 16 I C Bus Interface (IIC) 16.2 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I C bus interface. One of three pins can be specified as SCL and SDA input/output pin of each channel. Two or more input/output pins should not be specified for one channel.
Page 558: Register Descriptions
Section 16 I C Bus Interface (IIC) 16.3 Register Descriptions The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR.
Page 559: Slave Address Register (Sar)
Section 16 I C Bus Interface (IIC) If I C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS.
Page 560: Second Slave Address Register (Sarx)
Section 16 I C Bus Interface (IIC) 16.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave mode, when received address matches the second slave address, transmission/reception using the DTC is enabled.
Page 561: Table 16.2 Communication Format
Section 16 I C Bus Interface (IIC) Table 16.2 Communication Format SARX Operating Mode C bus format • SAR and SARX slave addresses recognized • General call address recognized C bus format • SAR slave address recognized • SARX slave address ignored •...
Page 562: C Bus Mode Register (Icmr)
Section 16 I C Bus Interface (IIC) 16.3.4 C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Bit Name Initial Value R/W Description MSB-First/LSB-First Select 0: MSB-first...
Page 563 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
Page 564: Table 16.3 I 2 C Transfer Rate
Section 16 I C Bus Interface (IIC) Table 16.3 I C Transfer Rate STCR ICMR Bits 5 and 6 Bit 5 Bit 4 Bit 3 Transfer Rate φ = 5 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz IICX CKS2 CKS1...
Page 565: C Bus Control Register (Iccr)
Section 16 I C Bus Interface (IIC) 16.3.5 C Bus Control Register (ICCR) ICCR controls the I C bus interface and performs interrupt flag confirmation. Bit Bit Name Initial Value R/W Description C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized.
Page 566 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1.
Page 567 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description BBSY R/W* Bus Busy Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode:...
Page 568 Section 16 I C Bus Interface (IIC) Bit Name Initial Value R/W Description IRIC R/(W)* C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
Page 569 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description IRIC R/(W) * Clocked synchronous serial format mode: • At the end of data transfer (rise of the 8th transmit/receive) • When a start condition is detected When the ICDRE or ICDRF flag is set to 1 in any operating mode: •...
Page 570: Table 16.4 Flags And Transfer States (Master Mode)
Section 16 I C Bus Interface (IIC) Tables 16.4 and 16.5 show the relationship between the flags and the transfer states. Table 16.4 Flags and Transfer States (Master Mode) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State 0↓ 0↓...
Page 571 Section 16 I C Bus Interface (IIC) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State 0↓ 0↓ — 1↑ — — — Arbitration lost — 0↓ — — — 0↓ Stop condition detected [Legend] 0-state retained 1-state retained —: Previous state retained ↓...
Page 572: Table 16.5 Flags And Transfer States (Slave Mode)
Section 16 I C Bus Interface (IIC) Table 16.5 Flags and Transfer States (Slave Mode) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State — Idle state (flag clearing required) 1↑ 0↓ — 1↑ Start condition detected 1↑/0 — 1↑...
Page 573 Section 16 I C Bus Interface (IIC) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State — — — — — — — Reception end with ICDRF=1 — — 0↓ 0↓ 0↓ — 0↓ — ICDR read with the above state 1↑/0 —...
Page 574: C Bus Status Register (Icsr)
Section 16 I C Bus Interface (IIC) 16.3.6 C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 16.4 and 16.5. Bit Bit Name Initial Value R/W Description ESTP R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode.
Page 575 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description AASX R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Page 576 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Page 577 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description ACKB Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE=1 in transmit mode [Clearing conditions] • When 0 is received as the acknowledge bit when ACKE=1 in transmit mode •...
Page 578: Ddc Switch Register (Ddcswr)
Section 16 I C Bus Interface (IIC) 16.3.7 DDC Switch Register (DDCSWR) DDCSWR controls IIC internal latch clearance. Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved The initial value should not be changed. — Reserved CLR3 IIC Clear 3 to 0...
Page 579: C Bus Extended Control Register (Icxr)
Section 16 I C Bus Interface (IIC) 16.3.8 C Bus Extended Control Register (ICXR) ICXR enables or disables the I C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit Bit Name Initial Value R/W Description STOPIM Stop Condition Interrupt Source Mask...
Page 580 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description ICDRF Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out.
Page 581 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description ICDRE Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete,...
Page 582 Section 16 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description ALIE Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost.
Page 583: Operation
Section 16 I C Bus Interface (IIC) 16.4 Operation The I C bus interface has an I C bus format and a serial format. 16.4.1 C Bus Data Format The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 16.3. The first frame following a start condition always consists of 9 bits.
Page 584: Figure 16.5 I C Bus Timing
Section 16 I C Bus Interface (IIC) 1–7 1–7 1–7 DATA DATA Figure 16.5 I C Bus Timing Table 16.6 I C Bus Data Format Symbols Legend Start condition. The master device drives SDA from high to low while SCL is high Slave address.
Page 585: Initialization
Section 16 I C Bus Interface (IIC) 16.4.2 Initialization Initialize the IIC by the procedure shown in figure 16.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) Cancel module stop mode (MSTPCRL) Enable the CPU accessing to the IIC control register and data register Set IICE = 1 in STCR Enable SAR and SARX to be accessed...
Page 586: Figure 16.7 Sample Flowchart For Operations In Master Transmit Mode
Section 16 I C Bus Interface (IIC) Start Initialize IIC [1] Initialization Read BBSY flag in ICCR [2] Test the status of the SCL and SDA lines. BBSY = 0? Set MST = 1 and [3] Select master transmit mode. TRS = 1 in ICCR Set BBSY =1 and [4] Start condition issuance...
Page 587 Section 16 I C Bus Interface (IIC) The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3.
Page 588: Figure 16.8 Example Of Operation Timing In Master Transmit Mode (Mls = Wait = 0)
Section 16 I C Bus Interface (IIC) 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Page 589: Master Receive Operation
Section 16 I C Bus Interface (IIC) Stop condition issuance (master output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (master output) [10] Data 1 Data 2 (slave output) ICDRE IRIC IRTR ICDR...
Page 590: Figure 16.10 Sample Flowchart For Operations In Master Receive Mode (Hnds = 1)
Section 16 I C Bus Interface (IIC) Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR [1] Select receive mode. Set HNDS = 1 in ICXR Clear IRIC flag in ICCR [2] Start receiving. The first read is a dummy read. Last receive? [5] Read the receive data (for the second and subsequent read) Read ICDR...
Page 591 Section 16 I C Bus Interface (IIC) The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
Page 592: Figure 16.11 Example Of Operation Timing In Master Receive Mode (Mls = Wait = 0, Hnds = 1)
Section 16 I C Bus Interface (IIC) Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 593 Section 16 I C Bus Interface (IIC) Receive Operation Using the Wait Function Figures 16.13 and 16.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Rev. 3.00 Jul. 14, 2005 Page 545 of 986 REJ09B0098-0300...
Page 594: Figure 16.13 Sample Flowchart For Operations In Master Receive Mode (Receiving Multiple Bytes) (Wait = 1)
Section 16 I C Bus Interface (IIC) Master receive mode Set TRS = 0 in ICCR [1] Select receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR [2] Start receiving.
Page 595: Figure 16.14 Sample Flowchart For Operations In Master Receive Mode (Receiving A Single Byte) (Wait = 1)
Section 16 I C Bus Interface (IIC) Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR [1] Select receive mode. Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 0 in ICMR Read ICDR [2] Start receiving.
Page 596 Section 16 I C Bus Interface (IIC) The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted.
Page 597 Section 16 I C Bus Interface (IIC) 11. Clear the IRIC flag to 0. 12. The IRIC flag is set to 1 in either of the following cases.  At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared.
Page 598: Figure 16.15 Example Of Master Receive Mode Operation Timing (Mls = Ackb = 0, Wait = 1)
Section 16 I C Bus Interface (IIC) Master tansmit mode Master receive mode (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (slave output) Data 1 Data 2...
Page 599: Slave Receive Operation
Section 16 I C Bus Interface (IIC) 16.4.5 Slave Receive Operation In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address.
Page 600: Figure 16.17 Sample Flowchart For Operations In Slave Receive Mode (Hnds = 1)
Section 16 I C Bus Interface (IIC) Slave receive mode Initialize IIC [1] Initialization. Select slave receive mode. Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Clear IRIC flag in ICCR ICDRF = 1?
Page 601 Section 16 I C Bus Interface (IIC) The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0.
Page 602: Figure 16.18 Example Of Slave Receive Mode Operation Timing (1) (Mls = 0, Hnds= 1)
Section 16 I C Bus Interface (IIC) Start condition generation [7] SCL is fixed low until ICDR is read (Pin waveform) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output)
Page 603: Figure 16.19 Example Of Slave Receive Mode Operation Timing (2) (Mls = 0, Hnds= 1)
Section 16 I C Bus Interface (IIC) Stop condition generation [7] SCL is fixed low until ICDR is read [7] SCL is fixed low until ICDR is read (master output) (slave output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 604: Figure 16.20 Sample Flowchart For Operations In Slave Receive Mode (Hnds = 0)
Section 16 I C Bus Interface (IIC) Slave receive mode Set MST = 0 and TRS = 0 in ICCR [1] Select slave receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR [2] Read the receive data remaining unread.
Page 605 Section 16 I C Bus Interface (IIC) The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0.
Page 606: Figure 16.21 Example Of Slave Receive Mode Operation Timing (1) (Mls = Ackb = 0, Hnds = 0)
Section 16 I C Bus Interface (IIC) Start condition issuance (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 (master output) Slave address Data 1 (slave output) IRIC...
Page 607: Slave Transmit Operation
Section 16 I C Bus Interface (IIC) 16.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode.
Page 608 Section 16 I C Bus Interface (IIC) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1.
Page 609: Figure 16.24 Example Of Slave Transmit Mode Operation Timing (Mls = 0)
Section 16 I C Bus Interface (IIC) 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1.
Page 610: Iric Setting Timing And Scl Control
Section 16 I C Bus Interface (IIC) 16.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock.
Page 611: Figure 16.26 Iric Setting Timing And Scl Control (2)
Section 16 I C Bus Interface (IIC) When WAIT = 1, and FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. IRIC User processing Write to ICDR (transmit)
Page 612: Figure 16.27 Iric Setting Timing And Scl Control (3)
Section 16 I C Bus Interface (IIC) When FS = 1 and FSX = 1 (clocked synchronous serial format) IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. IRIC User processing Clear IRIC Write to ICDR (transmit) Clear IRIC or read from ICDR (receive)
Page 613: Operation By Using Dtc
Section 16 I C Bus Interface (IIC) 16.4.8 Operation by Using DTC This LSI provides the DTC to allow consecutive transfer. The DTC is activated when the IRTR flag which is one of two interrupt flags (IRIC and IRTR) is set to 1. When the ACKE bit is cleared to 0, regardless of the acknowledge bit, the ICDRE, IRIC, and IRTR flags are set at the completion of the data transfer.
Page 614: Table 16.7 Operation By Using Dtc
Section 16 I C Bus Interface (IIC) Table 16.7 Operation by Using DTC Master Transmit Master Receive Slave Transmit Slave Receive Item Mode Mode Mode Mode Slave address + Transmission by Transmission by Reception by CPU Reception by CPU R/W bit DTC (ICDR write) CPU (ICDR write) (ICDR read)
Page 615: Noise Canceller
Section 16 I C Bus Interface (IIC) 16.4.9 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 16.28 shows a block diagram of the noise canceller. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 616: 16.4.10 Initialization Of Internal State
Section 16 I C Bus Interface (IIC) 16.4.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit.
Page 617: Interrupt Sources
Section 16 I C Bus Interface (IIC) • If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system.
Page 618: Usage Notes
Section 16 I C Bus Interface (IIC) 16.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I C bus, neither condition will be output correctly.
Page 619: Table 16.10 Permissible Scl Rise Time
Section 16 I C Bus Interface (IIC) 4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle t , as shown in section 26, Electrical Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz.
Page 620 Section 16 I C Bus Interface (IIC) Table 16.11 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Specifi- φ = φ = φ = φ = φ = Influence cation (Max.) 5 MHz 16 MHz...
Page 621: Figure 16.29 Notes On Reading Master Receive Data
Section 16 I C Bus Interface (IIC) 7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Page 622: Figure 16.30 Flowchart For Start Condition Issuance Instruction For Retransmission And
Section 16 I C Bus Interface (IIC) Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 8. Notes on start condition issuance for retransmission Figure 16.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart.
Page 623: Figure 16.31 Stop Condition Issuance Timing
Section 16 I C Bus Interface (IIC) Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 9. Note on when I C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
Page 624: Figure 16.32 Iric Flag Clearing Timing When Wait = 1
Section 16 I C Bus Interface (IIC) 10. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be inserted by driving the SCL pin low is used when the wait function is used in I C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below.
Page 625: Figure 16.33 Icdr Read And Iccr Access Timing In Slave Transmit Mode
Section 16 I C Bus Interface (IIC) 11. Note on ICDR read and ICCR access in slave transmit mode In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 16.33. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling.
Page 626: Figure 16.34 Trs Bit Set Timing In Slave Mode
Section 16 I C Bus Interface (IIC) 12. Note on TRS bit setting in slave mode In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 16.34), the bit value becomes valid immediately when it is set.
Page 627 Section 16 I C Bus Interface (IIC) 13. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly.
Page 628: Module Stop Mode Setting
Section 16 I C Bus Interface (IIC) • Arbitration is lost • The AL flag in ICSR is set to 1 C bus interface DATA1 (Master transmit mode) Transmit data match Transmit data does not match Transmit timing match Other device DATA2 DATA3 (Master transmit mode)
Page 629: Section 17 Keyboard Buffer Control Unit (Kbu)
Section 17 Keyboard Buffer Control Unit (KBU) Section 17 Keyboard Buffer Control Unit (KBU) This LSI has three on-chip keyboard buffer control unit (KBU) channels. The KBU is provided with functions conforming to the PS/2 interface specifications. Data transfer using the KBU employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc.
Page 630: Figure 17.1 Block Diagram Of Kbu
Section 17 Keyboard Buffer Control Unit (KBU) Internal data bus KBBR KBTR Transmission start KBCR1 (PS2AD, PS2BD, KCLKI KBCRH Control PS2CD) logic Parity KCLK Transmit counter (PS2AC, nalue KBCR2 PS2BC, PS2CC) KBCRL KCLKO Register counter value KBI interrupt KCI interrupt KTI interrupt [Legend] KBU data I/O pin...
Page 631: Figure 17.2 Kbu Connection
Section 17 Keyboard Buffer Control Unit (KBU) Figure 17.2 shows how the KBU is connected. System side Keyboard side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer control unit (This LSI) Figure 17.2 KBU Connection Rev.
Page 632: Input/Output Pins
Section 17 Keyboard Buffer Control Unit (KBU) 17.2 Input/Output Pins Table 17.1 lists the input/output pins used by the keyboard buffer control unit. Table 17.1 Pin Configuration Channel Name Abbreviation* Function KBU clock I/O pin (KCLK0) PS2AC KBU clock input/output KBU data I/O pin (KD0) PS2AD KBU data input/output...
Page 633: Register Descriptions
Section 17 Keyboard Buffer Control Unit (KBU) 17.3 Register Descriptions The KBU has the following registers for each channel. • Keyboard control register 1 (KBCR1) • Keyboard control register 2 (KBCR2) • Keyboard control register H (KBCRH) • Keyboard control register L (KBCRL) •...
Page 634 Section 17 Keyboard Buffer Control Unit (KBU) Bit Name Initial Value Description KTIE Transmit Completion Interrupt Enable Selects whether a transmit completion interrupt is enabled or disabled. 0: Disables transmit completion interrupt 1: Enables transmit completion interrupt   Reserved The initial value should not be changed.
Page 635: Keyboard Buffer Control Register 2 (Kbcr2)
Section 17 Keyboard Buffer Control Unit (KBU) 17.3.2 Keyboard Buffer Control Register 2 (KBCR2) KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK. Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD (LSB-first).
Page 636: Keyboard Control Register H (Kbcrh)
Section 17 Keyboard Buffer Control Unit (KBU) 17.3.3 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer control unit. Bit Name Initial Value Description KBIOE Keyboard In/Out Enable Selects whether or not the keyboard buffer control unit is used.
Page 637 Section 17 Keyboard Buffer Control Unit (KBU) Bit Name Initial Value Description KBIE Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer control unit to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR.
Page 638: Keyboard Control Register L (Kbcrl)
Section 17 Keyboard Buffer Control Unit (KBU) 17.3.4 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer control unit pin output. Bit Name Initial Value Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled KCLKO...
Page 639 Section 17 Keyboard Buffer Control Unit (KBU) Bit Name Initial Value Description RXCR3 Receive Counter RXCR2 These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be RXCR1 modified. RXCR0 The receive counter is initialized by a reset and when 0 is written in KBE.
Page 640: Keyboard Data Buffer Register (Kbbr)
Section 17 Keyboard Buffer Control Unit (KBU) 17.3.5 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit Name Initial Value Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset, in hardware standby mode or when KBIOE is cleared to 0.
Page 641: Operation
Section 17 Keyboard Buffer Control Unit (KBU) 17.4 Operation 17.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 642: Figure 17.3 Sample Receive Processing Flowchart
Section 17 Keyboard Buffer Control Unit (KBU) Start [1] Set the KBIOE bit to 1 in Set KBIOE bit KBCRL. [2] Read KBCRH, and if the Read KBCRH KCLKI and KDI bits are both 1, set the KBE bit KCLKI (receive enabled state).
Page 643: Transmit Operation
Section 17 Keyboard Buffer Control Unit (KBU) Flag cleared Receive processing/ error handling KCLK (pin state) Start Parity bit Stop bit (pin state) KCLK (input) KCLK Automatic I/O inhibit (output) Previous data Receive data KB7 to KB0 [1] [2] [3] [4] [5] Figure 17.4 Receive Timing 17.4.2...
Page 644: Figure 17.5 Sample Transmit Processing Flowchart
Section 17 Keyboard Buffer Control Unit (KBU) Start (Condition: KBE = 0) Write 1 to the KBIOE bit to enable transmission/ Set KBIOE bit reception. Clear KBE bit Clear the KBE bit (reception disabled). (reception disabled) Write transmit data Write transmit data to KBTR. to KBTR Read KBCRH, and when both the KCLKI and Read KBCRH...
Page 645: Receive Abort
Section 17 Keyboard Buffer Control Unit (KBU) I/O inhibit KCLK (pin state) Receive completed Stop bit Start bit Parity notification (pin state) KCLK (input) I/O inhibit KCLK (output) KBTE KTER KBTS [9] [10] [11] [6] [7] [8] [1] to [3] Figure 17.6 Transmit Timing 17.4.3 Receive Abort...
Page 646: Figure 17.7 (1) Sample Receive Abort Processing Flowchart
Section 17 Keyboard Buffer Control Unit (KBU) [1] Read KBCRL, and if KBF = 1, Start perform processing 1. [2] Read KBCRH, and if the value of Receive state bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort Read KBCRL reception.
Page 647: Figure 17.7 (2) Sample Receive Abort Processing Flowchart
Section 17 Keyboard Buffer Control Unit (KBU) Processing 1 [1] On the system side, drive the KCLK pin low, Receive operation ends setting the I/O inhibit state. normally Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted.
Page 648: Kclki And Kdi Read Timing
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.4 KCLKI and KDI Read Timing Figure 17.9 shows the KCLKI and KDI read timing. φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) The φ clock shown here is scaled by 1/N in medium-speed mode when the operating Note:* mode is active mode.
Page 649: Kclko And Kdo Write Timing
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.5 KCLKO and KDO Write Timing Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. φ* Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) The φ...
Page 650: Kbf Setting Timing And Kclk Control
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.6 KBF Setting Timing and KCLK Control Figure 17.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK 11th fall (pin) Internal KCLK Falling edge signal RXCR3 to B'1010 B'0000 RXCR0 KCLK Automatic I/O inhibit...
Page 651: Receive Timing
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.7 Receive Timing Figure 17.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to N + 1 N + 2 RXCR0 Internal KD (KDI) KBBR7 to KBBR0 The φ...
Page 652: Operation During Data Reception
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.8 Operation during Data Reception If the KBS bit in KBCRH is set to 1 with other keyboard buffer control units in reception*, the KCLK is automatically pulled down. Figure 17.13 shows receive timing and the KCLK. Note: * Period from the first falling edge of KCLK to completion of reception (KBF = 1).
Page 653: Kclk Fall Interrupt Operation
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.9 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRH to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 17.14 shows the setting method and an example of operation.
Page 654: 17.4.10 First Kclk Falling Interrupt
Section 17 Keyboard Buffer Control Unit (KBU) 17.4.10 First KCLK Falling Interrupt An interrupt can be generated by detecting the first falling edge of KCLK on reception and transmission. Software standby, watch, and subsleep modes can be cancelled by a first KCLK falling interrupt.
Page 655 Section 17 Keyboard Buffer Control Unit (KBU) • Canceling software standby mode, watch mode, and subsleep mode Software standby, watch, and subsleep modes are cancelled by a first KCLK falling interrupt. In this case, an interrupt is generated at the first KCLK since software standby mode, watch mode, or subsleep mode has been shifted (figure 17.17).
Page 656: Figure 17.16 First Kclk Interrupt Path
Section 17 Keyboard Buffer Control Unit (KBU) Software standby mode, watch mode, subsleep mode Interrupt control block Falling edge detection circuit Interrupt KCLK Interrupt request vector to CPU generation circuit Interrupt control Figure 17.16 First KCLK Interrupt Path Rev. 3.00 Jul. 14, 2005 Page 608 of 986 REJ09B0098-0300...
Page 657: Figure 17.17 Interrupt Timing In Software Standby Mode, Watch Mode, And Subsleep Mode
Section 17 Keyboard Buffer Control Unit (KBU) (a) Interrupt timing in software standby mode, watch mode, and subsleep mode KCLK Software standby mode, watch mode, subsleep internal signal Interrupt internal signal Interrupt generated (b) When a transition to software standby mode, watch mode, or subsleep mode is performed while the KCLI is high KCLK Software standby mode, watch mode,...
Page 658: Figure 17.18 Internal Flag Of First Kclk Falling Interrupt In Software Standby Mode, Watch Mode, And Subsleep Mode
Section 17 Keyboard Buffer Control Unit (KBU) KCLK First KCLK falling edge Automatic clear Internal flag Interrupt generated Interrupt accepted (Accepted at any timing) Figure 17.18 Internal Flag of First KCLK Falling Interrupt in Software Standby mode, Watch mode, and Subsleep mode Rev.
Page 659: Usage Notes
Section 17 Keyboard Buffer Control Unit (KBU) 17.5 Usage Notes 17.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected.
Page 660: Kd Output By Kdo Bit (Kbcrl) And By Automatic Transmission
Section 17 Keyboard Buffer Control Unit (KBU) 17.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission Figure 17.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the automatic transmission. Switch to the KD output by the automatic transmission is performed when KBTS is set to 1 and TXCR is not cleared to 0.
Page 661: Section 18 Lpc Interface (Lpc)
Section 18 LPC Interface (LPC) Section 18 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC includes four register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock.
Page 662 Section 18 LPC Interface (LPC) • Supports LPC/FW memory cycles  Supports LPC memory read, LPC memory write, FW memory read, and FW memory write cycle transfer  FW memory read and FW memory write cycles can be transferred in bytes/words/longwords ...
Page 663: Figure 18.1 Block Diagram Of Lpc
Section 18 LPC Interface (LPC) Figure 18.1 shows a block diagram of the LPC. LDRQ Module data bus DLDRQ Parallel → serial conversion TWR0MW IDR4 SERIRQ IDR3 TWR1 to DSERIRQ TWR15 IDR2 SIRQCR0 IDR1 CLKRUN SIRQCR1 PTCNT2 Cycle detection SIRQCR2 DCLKRUN DLAD0 to Control logic...
Page 664: Input/Output Pins
Section 18 LPC Interface (LPC) 18.2 Input/Output Pins Table 18.1 lists the LPC pin configuration. Table 18.1 Pin Configuration Name Abbreviation Port Function LPC address/ LAD3 to LAD0 P33 to P30 I/O Cycle type/address/data signals data 3 to 0 serially (4-signal-line) transferred in synchronization with LCLK LFRAME LPC frame...
Page 665: Register Descriptions
Section 18 LPC Interface (LPC) Name Abbreviation Port Function LPC Encoded LDRQ Output* DMA request signal DMA request Docking LPC DLDRQ Input* DMA request signal Encoded DMA request Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function.
Page 666 Section 18 LPC Interface (LPC) • Host base address registers 1H and 1L (HBAR1H, HBAR1L) • Host base address registers 2H and 2L (HBAR2H, HBAR2L) • On-chip RAM host base address registers H and L (RAMBARH, RAMBARL) • Address space set register (ASSR) •...
Page 667: Host Interface Control Registers 0 And 1 (Hicr0 And Hicr1)
Section 18 LPC Interface (LPC) 18.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface.
Page 668 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  FGA20E Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. When the fast Gate A20 is disabled, the normal Gate A20 can be implemented by firmware controlling P81 output.
Page 669 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  PMEE PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed. PMEE PMEB : PME output disabled, other...
Page 670 Section 18 LPC Interface (LPC) • HICR1 Bit Name Initial Value Slave Host Description  LPCBSY LPC Busy Indicates that the LPC interface is processing a transfer cycle. 0: LPC interface is in transfer cycle wait state • Bus idle, or transfer cycle not subject to processing is in progress •...
Page 671 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  CLKREQ 0 LCLK Request Indicates that the LPC interface’s SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] • LPC hardware reset or LPC software reset •...
Page 672 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  LRSTB LPC Software Reset Bit Resets the LPC interface. For the scope of initialization by an LPC reset, see section 18.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] •...
Page 673: Host Interface Control Registers 2 And 3 (Hicr2 And Hicr3)
Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  LSMIB LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0.  LSCIB LSCI output Bit Controls LSCI output in combination with the LSCIE bit.
Page 674 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description R/(W)*  SDWN LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. 0: [Clearing conditions] •...
Page 675 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IBFIE3 IDR3 and TWR Receive Complete interrupt Enable Enables or disables IBFI3 interrupt to the slave (this LSI). 0: Input data register IDR3 and TWR receive complete interrupt requests disabled 1: [When TWRIE = 0 in LADR3] Input data register (IDR3) receive complete interrupt requests enabled...
Page 676: Host Interface Control Register 4 (Hicr4)
Section 18 LPC Interface (LPC) • HICR3 Bit Name Initial Value Slave Host Description LFRAME Pin Monitor  LFRAME Undefined CLKRUN Pin Monitor  CLKRUN Undefined  SERIRQ Undefined SERIRQ Pin Monitor LRESET Pin Monitor  LRESET Undefined LPCPD Pin Monitor ...
Page 677: Lpc Channel 3 Address Registers H And L (Ladr3H And Ladr3L)
Section 18 LPC Interface (LPC) 18.3.4 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L) LADR3 stores the LPC channel 3 host address and controls the operation of the bidirectional data registers. The contents of the address fields in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Page 678 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  TWRE Bidirectional Data Register Enable Enables or disables bidirectional data register operation. 0: TWR operation is disabled TWR-related I/O address match determination is halted 1: TWR operation is enabled When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3.
Page 679: Lpc Channel 4 Address Registers H And L (Ladr4H And Ladr4L)
Section 18 LPC Interface (LPC) 18.3.5 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L) LADR4 stores the LPC channel 4 host address. The LADR4 contents must not be changed while channel 4 is operating (while LPC4E is set to 1). •...
Page 680: Input Data Registers 1 To 4 (Idr1 To Idr4)
Section 18 LPC Interface (LPC) • Host select register I/O Address Transfer Cycle Bits 5 to 3 Bit 2 Bits 1 and 0 Host Select Register Bits 15 to 3 in LADR4 Bits 1 and 0 in LADR4 I/O write IDR4 write (data) Bits 15 to 3 in LADR4 Bits 1 and 0 in LADR4...
Page 681: Output Data Registers 1 To 4 (Odr1 To Odr4)
Section 18 LPC Interface (LPC) 18.3.7 Output Data Registers 1 to 4 (ODR1 to ODR4) ODR1 to ODR4 are 8-bit readable/writable registers for the slave (this LSI), and 8-bit read-only registers for the host. The registers selected from the host according to the I/O address are shown in the following table.
Page 682: Status Registers 1 To 4 (Str1 To Str4)
Section 18 LPC Interface (LPC) 18.3.9 Status Registers 1 to 4 (STR1 to STR4) STR1 to STR4 are 8-bit registers that indicate status information during LPC interface processing. The registers selected from the host according to the I/O address are shown in the following table. For information on STR3 and STR4 selection, see the section of the corresponding LADR.
Page 683 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description IBF1 Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). The IBF1 flag setting and clearing conditions are different when the fast Gate A20 is used.
Page 684 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description IBF2 Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR2 1: [Setting condition] When the host writes to IDR2 in I/O write cycle OBF2 R/(W)* R Output Buffer Full...
Page 685 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description MWMF Master Write Mode Flag 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR0 in I/O write cycle while SWMF = 0 SWMF R/(W)* R Slave Write Mode Flag...
Page 686 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description OBF3A R/(W)* R Output Buffer Full 0: [Clearing conditions] • When the host reads ODR3 in I/O read cycle • When the slave writes 0 to the OBF3 bit 1: [Setting condition] •...
Page 687 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description OBF3 R/(W)* R Output Buffer Full 0: [Clearing conditions] • When the host reads ODR3 in I/O read cycle • When the slave writes 0 to the OBF3 bit 1: [Setting condition] •...
Page 688: Serirq Control Register 0 (Sirqcr0)
Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description OBF4 R/(W)* R Output Buffer Full 0: [Clearing conditions] • When the host reads ODR4 in I/O read cycle • When the slave writes 0 to the OBF3 bit 1: [Setting condition] •...
Page 689 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SELREQ 0 Start Frame Initiation Request Select Selects the condition of a start frame initiation request when a host interrupt request is cleared in quiet mode. 0: Start frame initiation is requested when all interrupt requests are cleared 1: Start frame initiation is requested when one or more interrupt requests are cleared...
Page 690 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE3A Host SMI Interrupt Enable 3A Enables or disables an SMI interrupt request when OBF3A is set by an ODR3 write. 0: Host SMI interrupt request by OBF3A and SMIE3A is disabled [Clearing conditions] •...
Page 691 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ12E1 0 Host IRQ12 Interrupt Enable 1 Enables or disables an HIRQ12 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] •...
Page 692: Serirq Control Register 1 (Sirqcr1)
Section 18 LPC Interface (LPC) 18.3.11 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. Bit Name Initial Value Slave Host Description  IRQ11E3 0 Host IRQ11 Interrupt Enable 3 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write.
Page 693 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ10E3 0 Host IRQ10 Interrupt Enable 3 Enables or disables an HIRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ10 interrupt request by OBF3A and IRQE10E3 is disabled [Clearing conditions] •...
Page 694 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ6E3 Host IRQ6 Interrupt Enable 3 Enables or disables an HIRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ6 interrupt request by OBF3A and IRQE6E3 is disabled [Clearing conditions] •...
Page 695 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ10E2 0 Host IRQ10 Interrupt Enable 2 Enables or disables an HIRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ10 interrupt request by OBF2 and IRQE10E2 is disabled [Clearing conditions] •...
Page 696 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ6E2 Host IRQ6 Interrupt Enable 3 Enables or disables an HIRQ6 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ6 interrupt request by OBF2 and IRQE6E2 is disabled [Clearing conditions] •...
Page 697: Serirq Control Register 2 (Sirqcr2)
Section 18 LPC Interface (LPC) 18.3.12 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs. Bit Name Initial Value Slave Host Description  IEDIR3 Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable...
Page 698 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ11E4 0 Host IRQ11 Interrupt Enable 4 Enables or disables an HIRQ11 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ11 interrupt request by OBF4 and IRQE11E4 is disabled [Clearing conditions] •...
Page 699 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E4 Host IRQ9 Interrupt Enable 4 Enables or disables an HIRQ9 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ9 interrupt request by OBF4 and IRQE9E4 is disabled [Clearing conditions] •...
Page 700 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE4 Host SMI Interrupt Enable 4 Enables or disables an SMI interrupt request when OBF4 is set by an ODR4 write. 0: Host SMI interrupt request by OBF4 and SMIE4 is disabled [Clearing conditions] •...
Page 701: Host Interface Select Register (Hisel)
Section 18 LPC Interface (LPC) 18.3.13 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame. Initial Bit Name Value Slave Host Description ...
Page 702: Ram Buffer Address Register (Rbufar)
Section 18 LPC Interface (LPC) 18.3.14 RAM Buffer Address Register (RBUFAR) RBUFAR stores the start address of 256-byte buffer in the on-chip RAM used for the flash memory programming in an LPC/FW memory cycle. The flash memory is programmed in units of 128 bytes.
Page 703: Flash Memory Programming Address Registers H And L
Section 18 LPC Interface (LPC) 18.3.15 Flash Memory Programming Address Registers H and L (FLWARH and FLARL) FLWAR stores the start address of the flash memory programming in an LPC/FW memory cycle. Bits 19 to 7 of the start address set by the FLWAR set command are stored in this register. Bits 23 to 20 of the address are fixed H'0, and 6 to 0 are fixed H'00.
Page 704: Manufacture Id Code Register (Lmcmidcr) And Device Id Code Register (Lmcdidcr)
Section 18 LPC Interface (LPC) 18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register (LMCDIDCR) LMCMIDCR and LMCDIDCR store the manufacture ID code and device ID code, respectively. The contents of start address of LMCMIDCR and LMCDIDCR are output in response to the ID read command.
Page 705: Erase Block Register (Eblkr)
Section 18 LPC Interface (LPC) 18.3.17 Erase Block Register (EBLKR) EBLKR stores a block number set by the block erasure command. Bit Name Initial Value Slave Host Description Bit 7 Store a block number ranging from 0 to 23. The block number is specified in BCD code (binary coded Bit 6 decimal code).
Page 706: Lmc Status Registers 1 And 2 (Lmcst1 And Lmcst2)
Section 18 LPC Interface (LPC) 18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2) LMCST1 and LMCST2 indicate the processing status of the LMC. The contents of LMCST1 and LMCST2 are output in response to the status read command. For details of the status read command, see section 18.4.8, LPC/FW Memory Access Command.
Page 707 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description BUFINII R/(W)* 128-Byte Buffer Initialization Interrupt/End Flag Setting this bit by the buffer initialization command generates a BUFINII interrupt (LMCI). 0: Buffer initialization command wait Buffer initialization end [Clearing condition] When writing 0 after reading BUFINII = 1 1: Buffer initialization is in progress...
Page 708 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description FLEERR R/(W)* Flash Memory Erasing Error 0: Flash memory has been completed erasure [Clearing condition] Clearing by the clear status command 1: Flash memory erasing error has been occurred ...
Page 709 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description ERASEE Enables/disables the block erasure command 0: Disables the block erasure command [Clearing conditions] • Clearing by the block erasure command • Clearing by the clear status command 1: Enables the block erasure command [Setting condition] •...
Page 710: Lmc Control Registers 1 And 2 (Lmccr1 And Lmccr2)
Section 18 LPC Interface (LPC) 18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2) LMCCR1 enables/disables the LMC host interface function. LMCCR2 enables/disables interrupts requested from the host by the interrupt commands and selects wait-state type. • LMCCR1 Bit Name Initial Value Slave Host Description ...
Page 711 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  FLASHE Flash Memory Programming/Erasing Enable Enables/disables to program/erase the flash memory by the LPC/FW memory cycle. Programming/erasing the flash memory is controlled in combination with the FLPIE and FLEIE bits by the flash memory programming/erasing command.
Page 712 Section 18 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  BUFINIIE 0 RAM Buffer Initialization Interrupt Enable (LMCI) 0: Disables the RAM buffer initialization command receive complete interrupt 1: Enables the RAM buffer initialization command receive complete interrupt ...
Page 713: Host Base Address Registers 1H And 1L (Hbar1H And Hbar1L)
Section 18 LPC Interface (LPC) 18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L) HBAR1 stores the upper 16 bits of a host start address when a host address is translated into a flash memory address. The inverted signal level of pin LID3 is reflected in the MSB of HBAR1. The lower 16 bits of the host start address are fixed H'0000.
Page 714: Host Base Address Registers 2H And 2L (Hbar2H And Hbar2L)
Section 18 LPC Interface (LPC) 18.3.21 Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L) HBAR2 stores the upper 16 bits of a host start address when a host address is translated into a flash memory address. The lower 16 bits of the host start address are fixed H'0000. The host address space to be translated is decided in combination with bits AS23 to AS20 in ASSR which select the size of the host address space.
Page 715: On-Chip Ram Host Base Address Registers H And L
Section 18 LPC Interface (LPC) 18.3.22 On-Chip RAM Host Base Address Registers H and L (RAMBARH and RAMBARL) RAMBAR stores the upper 16 bits of the host start address when a host address is translated into an on-chip RAM address. The lower 16 bits of the host start address are fixed H'0000. The host address space to be translated is decided in combination with the RAMASSR contents which select the size of the host address space.
Page 716: Address Space Set Register (Assr)
Section 18 LPC Interface (LPC) 18.3.23 Address Space Set Register (ASSR) ASSR selects the flash memory address space to be used by the host and slave. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). Bit Name Initial Value Slave Host Description ...
Page 717: On-Chip Ram Address Space Set Register (Ramassr)
Section 18 LPC Interface (LPC) 18.3.24 On-Chip RAM Address Space Set Register (RAMASSR) RAMASSR selects the on-chip RAM address space to be used by the host and slave. The bits 7 to 5 do not affect operations. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Page 718: Slave Address Register 1 (Sar1)
Section 18 LPC Interface (LPC) 18.3.25 Slave Address Register 1 (SAR1) SAR1 selects the slave start address of the flash memory obtained by translating the host address in HBAR1. The bits 23 to 16 are selected by this register. The lower 16 bits are fixed H'0000. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Page 719: Slave Address Register 2 (Sar2)
Section 18 LPC Interface (LPC) 18.3.26 Slave Address Register 2 (SAR2) SAR2 selects the upper eight bits of slave start address of the flash memory obtained by translating the host address in HBAR2. The lower 16 bits are fixed H'0000. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Page 720: Flash Memory Write Protect Registers H, M, And L
Section 18 LPC Interface (LPC) 18.3.28 Flash Memory Write Protect Registers H, M, and L (FWPRH, FWPRM, and FWPRL) FWPR controls the protect blocks of the flash memory to be accessed in LPC/FW memory write cycles. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Page 721 Section 18 LPC Interface (LPC) • FWPRM Bit Name Initial Value Slave Host Description  WPB15 Set to/clear the write protect blocks of the flash memory.  WPB14 WPB15 H'070000 to H'07FFFF  WPB13 WPB14 H'060000 to H'06FFFF  WPB12 WPB13 H'050000 to H'05FFFF ...
Page 722: Flash Memory Read Protect Registers H, M, And L
Section 18 LPC Interface (LPC) 18.3.29 Flash Memory Read Protect Registers H, M, and L (FRPRH, FRPRM, and FRPRL) FRPR controls the protect blocks of the flash memory to be accessed in LPC/FW memory read cycles. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Page 723 Section 18 LPC Interface (LPC) • FRPRM Bit Name Initial Value Slave Host Description  RPB15 Set to/clear the read protect blocks of the flash memory.  RPB14 RPB15 H'070000 to H'07FFFF  RPB13 RPB14 H'060000 to H'06FFFF  RPB12 RPB13 H'050000 to H'05FFFF ...
Page 724: On-Chip Ram Protect Control Register (Mpcr)
Section 18 LPC Interface (LPC) 18.3.30 On-Chip RAM Protect Control Register (MPCR) MPCR controls the access to the on-chip RAM in LPC/FW memory RW cycles. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). Bit Name Initial Value Slave Host Description 7 to 2 ...
Page 725: Operation
Section 18 LPC Interface (LPC) 18.4 Operation 18.4.1 LPC interface Activation The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in HICR0, LPC4E in HICR4, or LMCCR1 in LMCE. When the LPC interface is activated, the related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins.
Page 726: Table 18.2 Lpc I/O Cycle
Section 18 LPC Interface (LPC) In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B'0000 in the slave’s synchronization return cycle, but with the LPC of this LSI a value of B'0000 always returns.
Page 727: Figure 18.2 Typical Lframe Timing
Section 18 LPC Interface (LPC) LCLK LFRAME LAD3 to Start ADDR Sync Data Start LAD0 Cycle type, direction, and size Number of clocks Figure 18.2 Typical LFRAME Timing LCLK LFRAME Start ADDR Sync LAD3 to LAD0 Master will drive high Cycle type, Slave must stop driving direction,...
Page 728: Gate A20
Section 18 LPC Interface (LPC) 18.4.3 Gate A20 The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0.
Page 729: Figure 18.4 Ga20 Output
Section 18 LPC Interface (LPC) Start Host write H'D1 command received? Wait for next byte Host write Data byte? Write bit 1 of data byte to the bit of GA20 in DR Figure 18.4 GA20 Output Rev. 3.00 Jul. 14, 2005 Page 681 of 986 REJ09B0098-0300...
Page 730: Table 18.4 Fast Gate A20 Output Signals
Section 18 LPC Interface (LPC) Table 18.4 Fast Gate A20 Output Signals Internal CPU Interrupt Flag GA20 C/D1 Data/Command (IBF) (P81) Remarks H'D1 command Turn-on sequence 1 data* H'FF command Q (1) H'D1 command Turn-off sequence 0 data* H'FF command Q (0) H'D1 command Turn-on sequence...
Page 731: Lpc Interface Shutdown Function (Lpcpd)
Section 18 LPC Interface (LPC) 18.4.4 LPC Interface Shutdown Function (LPCPD) The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown.
Page 732: Table 18.5 Scope Of Lpc Interface Pin Shutdown
Section 18 LPC Interface (LPC) Table 18.5 shows the scope of the LPC interface pin shutdown. Table 18.5 Scope of LPC Interface Pin Shutdown Scope of Abbreviation Port Shutdown Notes LAD3 to LAD0 P33 to P30 Hi-Z LFRAME Input Hi-Z LRESET Input LPC hardware reset function is active...
Page 733: Table 18.6 Scope Of Initialization In Each Lpc Interface Mode
Section 18 LPC Interface (LPC) Table 18.6 Scope of Initialization in Each LPC interface Mode System Items Initialized Reset LPC Reset Shutdown LPC transfer cycle sequencer (internal state), LPCBSY and ABRT Initialized Initialized Initialized flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and Initialized Initialized Initialized...
Page 734: Figure 18.5 Power-Down State Termination Timing
Section 18 LPC Interface (LPC) System Items Initialized Reset LPC Reset Shutdown LRESET signal Input (port Input Input function LPCPD signal Input Input LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals Input Hi-Z PME, LSMI, LSCI, GA20 signals (when function is selected) Output Hi-Z PME, LSMI, LSCI, GA20 signals (when function is not selected)
Page 735: Lpc Interface Serialized Interrupt Operation (Serirq)
Section 18 LPC Interface (LPC) 18.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt.
Page 736: Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration
Section 18 LPC Interface (LPC) Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration Serial Interrupt Transfer Cycle Frame Drive Number Count Contents Source of States Notes Start Slave In quiet mode only, slave drive possible in first Host state, then next 3 states 0-driven by host IRQ0 Slave IRQ1...
Page 737: Lpc Interface Clock Start Request
Section 18 LPC Interface (LPC) In order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. For details see section 18.4.6, LPC Interface Clock Start Request. 18.4.6 LPC Interface Clock Start Request A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin.
Page 738: Table 18.8 Lpc Memory Cycle
Section 18 LPC Interface (LPC) address, or an on-chip memory is written after receiving an address and data. So, if a transfer cycle forced termination (abort) after receiving an address and data, an on-chip memory may be accessed. Table 18.8 LPC Memory Cycle LPC Memory Read Cycle LPC Memory Write Cycle State...
Page 739: Table 18.9 Fw Memory Cycle (Byte Transfer)
Section 18 LPC Interface (LPC) Table 18.9 FW Memory Cycle (Byte Transfer) FW Memory Read Cycle FW Memory Write Cycle State Drive Value Drive Value Count Contents Source (3 to 0) Contents Source (3 to 0) Start Host 1101 Start Host 1110 Device selection...
Page 740: Lpc/Fw Memory Access Command
Section 18 LPC Interface (LPC) 18.4.8 LPC/FW Memory Access Command An LPC/FW memory cycle with a special address can be used as a command. It allows to control flash memory erasure, programming and to read the status register of the flash memory. The host address space of which lower 16 bits are H'FFF0 to H'FFFF can be used as command space according to the RAMBAR setting.
Page 741: Table 18.10 List Of Lpc/Fw Memory Access Commands
Section 18 LPC Interface (LPC) Table 18.10 lists the LPC/FW memory access commands. Table 18.10 List of LPC/FW Memory Access Commands Wait Memory Command Operation Address Size Data State Access Interrupt Data read FL/RM B/W/L Read data ID read CMD0 CMD1 Status read CMD2...
Page 742 Section 18 LPC Interface (LPC) 2. ID read command When receiving the CMD0 or CMD1 address in an LPC/FW memory read cycle, the LPC sends back an MID/DID. Byte and word transfers are supported by the ID read command. In word transfer, an MID is sent back before a DID.
Page 743 Section 18 LPC Interface (LPC) 9. WRITEE clear command When receiving the CMD8 address in an LPC/FW memory write cycle, the LPC clears the WRITEE bit. Clearing the WRITEE bit avoids unintentional write accesses to the on-chip RAM. 10. FLWAR set command When receiving an FL address and the data of H'80 in an LPC/FW memory write cycle, the LPC stores the FL address in FLWAR and set the BUFTRAN bit to 1 for the data write command (flash memory).
Page 744 Section 18 LPC Interface (LPC) 14. Buffer initialization command When receiving the CMDB address in an LPC/FW memory write cycle, the LPC initializes the buffer. When BUFINIIE = 1, or BUFINIIE = 0 and HDINIE = 0, the LPC sets the BUFINII interrupt flag (one of the LMCI interrupt sources) to 1 on reception of the buffer initialization command.
Page 745: Table 18.11 List Of Factors That Prevents Sync Field Being Sent Back
Section 18 LPC Interface (LPC) Table 18.11 lists the factors that prevent the SYNC from being sent back in an LPC/FW memory read cycle. Table 18.11 List of Factors that Prevents SYNC Field being Sent Back Command Factor Remarks Common to all Start not match commands Device selection not match...
Page 746 Section 18 LPC Interface (LPC) Command Factor Remarks Data write On-chip RAM data write command WRITEE = 0 (on-chip RAM) disabled On-chip RAM write access disabled RAMWE = 0 O-chip memory access is in progress LMCBUSY = 1 Interrupt processing is in progress While following processes are in progress: •...
Page 747 Section 18 LPC Interface (LPC) Command Factor Remarks Flash memory FLWAR setting command not issued BUFTRAN = 0 programming On-chip memory access is in progress LMCBUSY = 1 Interrupt processing is in progress While following processes are in progress: • Programming flash memory (FLPI = 1) •...
Page 748: Flash Memory Address Translation (Host → Slave)
Section 18 LPC Interface (LPC) Flash Memory Address Translation (Host → Slave) 18.4.9 A host address is translated into a flash memory address by the settings of HBAR1, HBAR2, ASSR, SAR1, and SAR2. The slave address which exceeds H'0FFFFF must not be specified. The host addresses within the range of H'00000000 to H'FFFFFFFF are available for translation and the flash memory addresses within the range of H'000000 to H'0FFFFF are available.
Page 749: On-Chip Ram Address Translation (Host → Slave)
Section 18 LPC Interface (LPC) 1. Host address − HBAR1 = H'000FFFF0 − H'000E0000 = H'0001FFF0 2. H'0001FFF0 + SAR1 = H'0001FFF0 + H'050000 = H'06FFF0 (slave address) 18.4.10 On-Chip RAM Address Translation (Host → Slave) A host address is translated into an on-chip RAM address by the settings of RAMBAR, RAMSSR, and RAMAR.
Page 750: 18.4.11 Address Space Priority
Section 18 LPC Interface (LPC) 18.4.11 Address Space Priority The host addresses can be specified from H'00000000 to H'FFFF0000 by the settings of HBAR1, HBAR2, and RAMBAR. The host address spaces, however, may be overlapped depending on the ASSR setting. Moreover, the slave address spaces may be overlapped depending on the settings of SAR1, SAR2, and ASSR.
Page 751: 18.4.12 Example 1 Of Address Space Priority
Section 18 LPC Interface (LPC) 18.4.12 Example 1 of Address Space Priority Figure 18.11 shows an example of an address translation when the host address spaces are overlapped. When an address is translated with the settings shown in figure 18.11, host address spaces 1 and 2 are overlapped and host address space 2 and the on-chip RAM space are overlapped.
Page 752: 18.4.13 Example 2 Of Address Space Priority
Section 18 LPC Interface (LPC) 18.4.13 Example 2 of Address Space Priority Figure 18.12 shows another example of an address translation when the slave address spaces are overlapped. In the case of the settings shown in figure 18.12, slave address spaces 1 and 2 are overlapped.
Page 753: 18.4.14 Flash Memory Protection
Section 18 LPC Interface (LPC) 18.4.14 Flash Memory Protection To protect the flash memory contents, the flash memory is divided into blocks given in figure 18.13. Protection for each block can be enabled or disabled by the setting of the WPB or RPB bits. The write blocks are used in LPC/FW memory write cycles and the read blocks are used in LPC/FW memory read cycles.
Page 754: Figure 18.13 Flash Memory Protection
Section 18 LPC Interface (LPC) H'000000 4 kbytes (0) 4 kbytes (0) H'001000 4 kbytes (1) 4 kbytes (1) H'002000 4 kbytes (2) 4 kbytes (2) H'003000 4 kbytes (3) 4 kbytes (3) H'004000 32 kbytes (4) 32 kbytes (4) H'00C000 4 kbytes (5) 4 kbytes (5)
Page 755: 18.4.15 On-Chip Ram Protection
Section 18 LPC Interface (LPC) 18.4.15 On-Chip RAM Protection The on-chip RAM protection to the host access can be enabled or disabled by the setting of the RAMWE or RAMRE bits. The on-chip RAM is protected by the initial value. When accessing to the on-chip RAM, the protection must be disabled.
Page 756: Figure 18.15 Example Of Programming Flash Memory
Section 18 LPC Interface (LPC) Start [1] Specify the start address of buffer in the on-chip RAM used Initial settings for the flash memory programming (RBUFAR) etc. [2] Check LPC/FW memory write cycle processing state Read LMCST1 and LMCST2 Flag clear ? [3] Specify the start address of the user MAT programming Issue FLWAR setting command Read BUFTRAN bit...
Page 757: 18.4.17 Flash Memory Erasing
Section 18 LPC Interface (LPC) 18.4.17 Flash Memory Erasing Figure 18.16 shows a flowchart example of erasing the flash memory in the LPC/FW memory write cycle. Start Initial settings Read LMCST1 and LMCST2 [1] Check the LPC/FW memory write cycle processing state Flag clear? Issue erasing enable command [2] Enable erasing flash memory...
Page 758: Interrupt Sources
Section 18 LPC Interface (LPC) 18.5 Interrupt Sources 18.5.1 IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI The host has seven interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, LMC, LMCUI, and ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively.
Page 759: Smi, Hirq1, Hirq6, Hirq9, Hirq10, Hirq11, And Hirq12
Section 18 LPC Interface (LPC) 18.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 The LPC interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2, 3, or 4.
Page 760: Table 18.13 Hirq Setting And Clearing Conditions
Section 18 LPC Interface (LPC) Table 18.13 HIRQ Setting and Clearing Conditions Host Interrupt Setting Condition Clearing Condition HIRQ1 Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit IRQ1E1, (independent from bit IRQ1E1 and writes 1 or host reads ODR1 from IEDIR) HIRQ12...
Page 761: Figure 18.17 Hirq Flowchart (Example Of Channel 1)
Section 18 LPC Interface (LPC) Slave CPU Master CPU ODR1 write Interrupt initiation Write 1 to IRQ1E1 SERIRQ IRQ1 output SERIRQ IRQ1 ODR1 read source clear OBF1 = 0? All bytes transferred? Hardware operation Software operation Figure 18.17 HIRQ Flowchart (Example of Channel 1) Rev.
Page 762: Usage Note
Section 18 LPC Interface (LPC) 18.6 Usage Note 18.6.1 Data Conflict The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted.
Page 763: Module Stop Mode Setting
Section 18 LPC Interface (LPC) Table 18.14 Host Address Example Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 IDR3 H'A24A and H'A24E H'3FD0 and H'3FD4 ODR3 H'A24A H'3FD0 STR3 H'A24E H'3FD4 TWR0MW H'A250 H'3FC0 TWR0SW H'A250 H'3FC0 TWR1...
Page 764 Section 18 LPC Interface (LPC) Rev. 3.00 Jul. 14, 2005 Page 716 of 986 REJ09B0098-0300...
Page 765: Section 19 A/D Converter
Section 19 A/D Converter Section 19 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels to be selected. 19.1 Features • 10-bit resolution • Input channels: Eight analog input channels • Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as an analog reference voltage.
Page 766: Figure 19.1 Block Diagram Of A/D Converter
Section 19 A/D Converter Module data bus Internal data bus AVCC AVref 10-bit D/A AVSS φ/8 Comparator Control circuit φ/16 Sample-and-hold circuit ADI interrupt signal Conversion start trigger from TPU or 8-bit timer ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C...
Page 767: Input/Output Pins
Section 19 A/D Converter 19.2 Input/Output Pins Table 19.1 summarizes the pins used by the A/D converter. The eight analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1.
Page 768: Register Descriptions
Section 19 A/D Converter 19.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) •...
Page 769: A/D Control/Status Register (Adcsr)
Section 19 A/D Converter 19.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D converter operation. Bit Name Initial Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode •...
Page 770: A/D Control Register (Adcr)
Section 19 A/D Converter Bit Name Initial Value Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4...
Page 771: Operation
Section 19 A/D Converter 19.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion.
Page 772: Input Sampling And A/D Conversion Time
Section 19 A/D Converter 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion.
Page 773: Figure 19.2 A/D Conversion Timing
Section 19 A/D Converter φ Address Write signal Input sampling timing CONV [Legend] : ADCSR write cycle : ADCSR address : A/D conversion start delay : Input sampling time : A/D conversion time CONV Figure 19.2 A/D Conversion Timing Rev. 3.00 Jul. 14, 2005 Page 725 of 986 REJ09B0098-0300...
Page 774: External Trigger Input Timing
Section 19 A/D Converter Table 19.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1* Item Symbol Min. Typ. Max. Min. Typ. Max.   A/D conversion start delay time     Input sampling time  ...
Page 775: Interrupt Source
Section 19 A/D Converter 19.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. If the ADF bit in ADCSR has been set to 1 after A/D conversion ends and the ADIE bit is set to 1, an ADI interrupt request is enabled.
Page 776: Figure 19.4 A/D Conversion Accuracy Definitions
Section 19 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 19.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error...
Page 777: Usage Notes
Section 19 A/D Converter 19.7 Usage Notes 19.7.1 Permissible Signal Source Impedance This LSI’s analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 778: Setting Range Of Analog Power Supply And Other Pins
Section 19 A/D Converter 19.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤...
Page 779: Module Stop Mode Setting
Section 19 A/D Converter AVCC AVref 100 Ω AN0 to AN7 0.1 µF AVSS Notes: Values are reference values. 10 µF 0.01 µF : Input impedance Figure 19.7 Example of Analog Input Protection Circuit 10 kΩ To A/D converter AN0 to AN7 20 pF Note: Values are reference values.
Page 780 Section 19 A/D Converter Rev. 3.00 Jul. 14, 2005 Page 732 of 986 REJ09B0098-0300...
Page 781: Section 20 Ram
Section 20 RAM Section 20 RAM This LSI has 8 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 782 Section 20 RAM Rev. 3.00 Jul. 14, 2005 Page 734 of 986 REJ09B0098-0300...
Page 783: Section 21 Flash Memory (0.18-Μm F-Ztat Version)
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Section 21 Flash Memory (0.18-µm F-ZTAT Version) The flash memory has the following features. Figure 21.1 shows a block diagram of the flash memory. 21.1 Features • Size Product Classification ROM Size ROM Addresses H8S/2114R R4F2114R 1 Mbyte...
Page 784: Figure 21.1 Block Diagram Of Flash Memory
Section 21 Flash Memory (0.18-µm F-ZTAT Version)  User boot mode The user boot program of the optional interface can be made and the user MAT can be programmed. • Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection.
Page 785: Mode Transitions
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.1.1 Mode Transitions When each mode pin and the FWE pin are set in the reset state and the reset is started, this LSI enters each operating mode as shown in figure 21.2. •...
Page 786: Mode Comparison
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 21.1. Table 21.1 Comparison of Programming Modes User Program Programmer Boot Mode...
Page 787: Flash Memory Mat Configuration
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.1.3 Flash Memory MAT Configuration This LSI’s flash memory is configured by the 1-Mbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when program execution or data access is performed between two MATs, the MAT must be switched by using FMATS.
Page 788: Figure 21.4 Block Division Of User Mat (1)
Section 21 Flash Memory (0.18-µm F-ZTAT Version) → H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F Erase unit: 4 kbytes           H'000F80 H'000F81 H'000F82 H'000FFF Programming unit: 128 bytes → H'001000 H'001001 H'001002 H'00107F...
Page 789: Figure 21.4 Block Division Of User Mat (2)
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Programming unit: 128 bytes → EB12 H'040000 H'040001 H'040002 H'04007F Erase unit: 64 kbytes           H'04FF80 H'04FF81 H'04FF82 H'04FFFF Programming unit: 128 bytes → EB13 H'050000 H'050001...
Page 790: Programming/Erasing Interface
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows.
Page 791 Section 21 Flash Memory (0.18-µm F-ZTAT Version) 1. Selection of on-chip program to be downloaded For programming/erasing execution, set the FLSHE bit in STCR to 1 to make a transition to user program mode. This LSI has programming/erasing programs that can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface register.
Page 792: Input/Output Pins
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 5. Consecutive execution of programming/erasing When the 128-byte programming or one-block erasure does not end the processing, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program remains in the on-chip RAM even after the processing ends, download and initialization are not required when the same processing is executed consecutively.
Page 793: Table 21.3 Register/Parameter And Target Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) • Flash multipurpose address area (FMPAR) • Flash multipurpose data destination area (FMPDR) • Flash erase block select (FEBS) • Flash programming/erasing frequency control (FPEFEQ) There are several operating modes for accessing flash memory, for example, read mode/program mode.
Page 794: Programming/Erasing Interface Registers
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.3.1 Programming/Erasing Interface Registers The programming/erasing interface registers are all 8-bit registers that can be accessed in bytes. These registers are initialized at a reset or in hardware standby mode. • Flash Code Control Status Register (FCCS) FCCS is configured by bits which request monitoring of the FWE pin state and error occurrence during programming or erasing flash memory, and the download of an on-chip program.
Page 795 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Initial Bit Name Value Description FLER Flash Memory Error Indicates an error has occurred during programming or erasing flash memory. When this bit is set to 1, flash memory enters the error-protection state. In case this bit is set to 1, high voltage is applied to the internal flash memory.
Page 796 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Initial Bit Name Value Description (R)/W* Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR.
Page 797 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Initial Bit Name Value Description  7 to 1 All 0 Reserved The initial value should not be changed. PPVS Program Pulse Verify Selects the programming program.
Page 798 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • Flash Key Code Register (FKEY) FKEY is for software protection that enables download of an on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 to download an on-chip program or before executing the downloaded programming/erasing program, the key code must be written, otherwise the processing cannot be executed.
Page 799 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Initial Bit Name Value Description 0/1* MAT Select The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected when H'AA 0/1* is written.
Page 800 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address where an on-chip program is downloaded. This register must be specified before setting the SCO bit in FCCS to 1. Initial Bit Name Value...
Page 801: Programming/Erasing Interface Parameters
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.3.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. These parameters use the CPU general registers (ER0 and ER1) or the on-chip RAM area.
Page 802: Table 21.4 Parameters And Target Modes
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.4 Parameters and Target Modes Abbrevia- Down- Initializa- Program- Initial Parameter Name tion load tion ming Erasure R/W Value Allocation Ο    Undefined On-chip RAM* Download DPFR pass/fail result  Ο...
Page 803 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Initial Bit Name Value Description    7 to 3 Unused The return value is 0.  Source Select Error Detect Only one type can be specified for the on-chip program that can be downloaded. When more than two types of programs are selected, the program is not selected, or the program is selected without mapping, an error occurs.
Page 804 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. A pulse of the specified width must be applied when programming or erasing. The specified pulse width is made by the method in which a wait loop is configured by CPU instructions. The operating frequency of the CPU must be set too.
Page 805 Section 21 Flash Memory (0.18-µm F-ZTAT Version) (b) Flash pass/fail result parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the initialization result. Initial Bit Name Value Description    7 to 2 Unused The return value is 0.
Page 806 Section 21 Flash Memory (0.18-µm F-ZTAT Version) For details on the programming procedure, see section 21.4.2, User Program Mode. Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter stores the start address of the programming destination on the user MAT. When the address in an area other than the flash memory space is set, an error occurs.
Page 807 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Flash pass/fail result parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the programming processing result. Initial Bit Name Value Description    Unused The return value is 0. ...
Page 808 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Initial Bit Name Value Description  Flash Key Register Error Detect Returns the check result of the FKEY value before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is abnormal (FKEY = value other than H'5A) ...
Page 809 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program that is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block numbers 0 to 23.
Page 810 Section 21 Flash Memory (0.18-µm F-ZTAT Version) (b) Flash pass/fail result parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the erasing processing result. Initial Bit Name Value Description    Unused The return value is 0. ...
Page 811 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Initial Bit Name Value Description  Erase Block Select Error Detect Returns the check result whether the specified erase- block number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal ...
Page 812: On-Board Programming
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.4 On-Board Programming When the pins are set to on-board programming mode and the reset start is executed, a transition is made to an on-board programming state in which the on-chip flash memory can be programmed/erased.
Page 813: Figure 21.6 System Configuration In Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) This LSI Analysis execution Flash software memory (on-chip) Host Control command and program data Boot programming RxD1 On-chip tool and On-chip SCI_1 program data TxD1 Reply response Figure 21.6 System Configuration in Boot Mode SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI communication data (H'00) which is transmitted consecutively from the host.
Page 814: Table 21.6 System Clock Frequency For Automatic-Bit-Rate Adjustment By This Lsi
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI Bit Rate of Host System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI 4,800 bps 4 to 20 MHz 9,600 bps 4 to 20 MHz 19,200 bps 8 to 20 MHz State Transition Diagram...
Page 815: Figure 21.8 Overview Of Boot Mode State Transition Diagram
Section 21 Flash Memory (0.18-µm F-ZTAT Version) (Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Boot mode initiation Bit rate adjustment (reset in boot mode) Inquiry command reception Processing of Wait for inquiry inquiry setting setting command command Inquiry command response...
Page 816: User Program Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program built in the microcomputer beforehand. The programming/erasing overview flow is shown in figure 21.9.
Page 817: Figure 21.10 Ram Map When Programming/Erasing Is Executed
Section 21 Flash Memory (0.18-µm F-ZTAT Version) On-Chip RAM Address Map when Programming/Erasing is Executed Part of the procedure program that is made by the user, like the download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM.
Page 818: Figure 21.11 Programming Procedure
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 21.11. Start programming procedure program Select on-chip program Disable interrupts and to be downloaded and bus master operation specify download other than CPU destination by FTDAR...
Page 819 Section 21 Flash Memory (0.18-µm F-ZTAT Version) 128-byte programming is performed in one programming processing. To program more than 128 bytes, update the programming destination address/program data parameter in 128-byte units and repeat programming. When less than 128 bytes of programming is performed, the program data must amount to 128 bytes by filling in invalid data.
Page 820 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • The user MAT space is switched to the embedded program storage MAT. • After the selection condition of the download program and the FTDAR address setting are checked, the transfer processing to the on-chip RAM specified by FTDAR is executed. •...
Page 821 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Set the operating frequency to the FPEFEQ parameter for initialization. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register ER0). The settable range of the FPEFEQ parameter is 4 to 20 MHz. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed.
Page 822 Section 21 Flash Memory (0.18-µm F-ZTAT Version) CPU should be set to B'11 in interrupt control mode 1. This enables interrupts other than NMI to be held and not executed. The NMI interrupt must be masked within the user system. The interrupts that are held must be executed after all programming processings.
Page 823 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Programming There is an entry point for the programming program in the area from the start address of a download destination specified by FTDAR + 16 bytes. The subroutine is called and programming is executed by using the following steps.
Page 824: Figure 21.12 Erasing Procedure
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 21.12. Start erasing procedure program Select on-chip program to be downloaded and Disable interrupts and specify download bus master operation destination by FTDAR other than CPU...
Page 825 Section 21 Flash Memory (0.18-µm F-ZTAT Version) A single divided block is erased by one erasing processing. For block divisions, refer to figure 21.4. To erase two or more blocks, update the erase-block number and perform the erasing processing for each block. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1.
Page 826: Figure 21.13 Repeating Procedure Of Erasing And Programming
Section 21 Flash Memory (0.18-µm F-ZTAT Version) (d) The return value in the erasing program, FPFR (general register R0L) is determined. Determine whether erasure of the necessary blocks has completed. If more than one block is to be erased, update the FEBS parameter and repeat steps (b) to (e). Blocks that have already been erased can be erased again.
Page 827: User Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) In the above procedure, download and initialization are performed only once at the beginning. In this kind of operation, note the following: • Be careful not to damage on-chip RAM with overlapped settings. In addition to the erasing program area and programming program area, areas for the user procedure programs, work area, and stack area are allocated in the on-chip RAM.
Page 828: Figure 21.14 Procedure For Programming User Mat In User Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes.
Page 829 Section 21 Flash Memory (0.18-µm F-ZTAT Version) The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 21.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background.
Page 830: Figure 21.15 Procedure For Erasing User Mat In User Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes.
Page 831: Storable Areas For Procedure Program And Program Data
Section 21 Flash Memory (0.18-µm F-ZTAT Version) The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 21.15. MAT switching is enabled by writing a specific value to FMATS. Note however that while the MATs are being switched, the LSI is in an unstable state, e.g.
Page 832: Table 21.7 Executable Mat
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 6. After programming/erasing, access to the flash memory is prohibited until FKEY is cleared. In case the LSI mode is changed to generate a reset on completion of a programming/erasing operation, a reset state (RES = 0) of 100 µs or more must be secured. Transitions to the reset state or hardware standby mode are prohibited during programming/erasing operations.
Page 833: Table 21.8 (1) Usable Area For Programming In User Program Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.8 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-chip RAM User MAT User MAT Storage MAT Ο ×*   Storage area for program data Ο...
Page 834 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Storable/Executable Area Selected MAT Embedded Program Item On-chip RAM User MAT User MAT Storage MAT Ο × Ο Programming Ο × Ο Determination of programming result Ο × Ο Programming error processing Ο ×...
Page 835: Table 21.8 (2) Usable Area For Erasure In User Program Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.8 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-chip RAM User MAT User MAT Storage MAT Ο Ο Ο Selecting on-chip program to be downloaded Ο...
Page 836: Table 21.8 (3) Usable Area For Programming In User Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.8 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT Embedded On-chip User Boot User Boot Program Storage Item User MAT Ο ×*    Storage area for program data Ο...
Page 837 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Storable/Executable Area Selected MAT Embedded On-chip User Boot User Boot Program Storage Item User MAT Ο × Ο Setting programming parameter Ο × Ο Programming Ο × Ο Determination of programming result Ο ×* Ο...
Page 838: Table 21.8 (4) Usable Area For Erasure In User Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.8 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT Embedded On-chip User Boot User Boot Program Storage Item User MAT Ο Ο Ο Selecting on-chip program to be downloaded Ο...
Page 839: Protection
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Storable/Executable Area Selected MAT Embedded Program User Boot User Boot Storage Item |On-chip RAM User MAT Ο × Ο Erasure Ο × Ο Determination of erasure result Ο ×* Ο Erasing error processing Ο...
Page 840: Table 21.9 Hardware Protection
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.9 Hardware Protection Function to be Protected Programming/ Item Description Download Erasure  Ο FWE pin protection • When a low-level signal is input to the FWE pin, the FWE bit in FCCS is cleared and the programming/erasing protection state is entered.
Page 841: Software Protection
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.5.2 Software Protection Software protection is set up by disabling download of on-chip programming/erasing programs or by means of a key code. Table 21.10 Software Protection Function to be Protected Programming/ Item Description Download Erasure Ο...
Page 842: Figure 21.16 Transitions To Error-Protection State
Section 21 Flash Memory (0.18-µm F-ZTAT Version) • When a bus master other than the CPU, such as the DTC or LPC, gets the bus during programming/erasing Error protection is cancelled only by a reset or a transition to hardware-standby mode. Note that the reset should be released after a reset period of 100 µs which is longer than normal.
Page 843: Switching Between User Mat And User Boot Mat
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.6 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing.
Page 844: Programmer Mode
In programmer mode, a general PROM programmer that supports Renesas microcomputers with 1-Mbyte flash memory as a device type* can be used to freely write programs to the on-chip ROM. Programming/erasing is possible on the user MAT and user boot MAT* .
Page 845: Serial Communication Interface Specifications For Boot Mode
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.8 Serial Communication Interface Specifications for Boot Mode The boot program initiated in boot mode performs transmission and reception with the host PC via the on-chip SCI. The serial communication interface specifications for the host and boot program are shown below.
Page 846: Figure 21.19 Boot Program States
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Reset Bit-rate-adjustment state Inquiry/response Response wait Inquiry Inquiry and selection Response Transition to processing processing programming/erasing state Processing for erasing user MAT and user boot MAT Programming/erasing response wait Programming Erasing Checking Programming Erasing processing processing...
Page 847: Figure 21.20 Bit-Rate-Adjustment Sequence
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Bit-Rate-Adjustment State The bit rate is adjusted by measuring the period of a low-level byte (H'00) transmitted from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state.
Page 848: Figure 21.21 Communication Protocol Format
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 4. Programming of 128 bytes The size is not specified in the commands. The data size is indicated in the response to the programming unit inquiry. 5. Memory read response This response consists of r4 bytes of data. 1-byte command Command or response or 1-byte response...
Page 849: Table 21.11 Inquiry And Selection Commands
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Inquiry/Selection State The boot program returns information from the flash memory in response to the host’s inquiry commands and sets the device code, clock mode, and bit rate in response to the host’s selection command.
Page 850 Section 21 Flash Memory (0.18-µm F-ZTAT Version) All of these commands, except for boot program status inquiry (H'4F), will be valid until the boot program receives the programming/erasing state transition command (H'40). The host can choose the needed commands out of the above commands and make inquiries. The boot program status inquiry command (H'4F) remains valid even after the boot program has received the programming/erasing state transition command (H'40).
Page 851 Section 21 Flash Memory (0.18-µm F-ZTAT Version) (b) Device Selection The boot program will set the specified supported device in response to the device selection command. The program will return information on the selected device in response to the inquiry after this setting has been made.
Page 852 Section 21 Flash Memory (0.18-µm F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode in response to the clock mode selection command. The program will return information on the selected clock mode in response to the inquiry after this setting has been made.
Page 853 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Division Ratio Inquiry The boot program will return the supported division ratios in response to the division ratio inquiry command. Command H'22 • Command, H'22 (1 byte): Inquiry regarding division ratio Response H'32 Size Number of types...
Page 854 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values in response to the operating clock frequency inquiry command. Command H'23 • Command, H'23 (1 byte): Inquiry regarding operating clock frequencies Response H'33 Size...
Page 855 Section 21 Flash Memory (0.18-µm F-ZTAT Version) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses in response to the user boot MAT information inquiry command. Command H'24 • Command, H'24 (1 byte): Inquiry regarding user boot MAT information Response H'34 Size...
Page 856 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • Area start address (4 bytes): Start address of the area • Area last address (4 bytes): Last address of the area. There are as many groups of data representing the start and last addresses as there are areas. •...
Page 857 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • SUM (1 byte): Checksum (k) New Bit Rate Selection The boot program will set a new bit rate in response to the new bit rate selection command, and return the new bit rate in response to the confirmation. This new bit rate selection command should be sent after sending the clock mode selection command.
Page 858 Section 21 Flash Memory (0.18-µm F-ZTAT Version) • ERROR (1 byte): Error code H'11: Checksum error H'24: Bit rate selection error The rate is not available. H'25: Input frequency error The input frequency is not within the specified range. H'26: Division ratio error The division ratio does not match an available ratio.
Page 859: Figure 21.22 Sequence Of New Bit Rate Selection
Section 21 Flash Memory (0.18-µm F-ZTAT Version) φ × 10 ] − 1} × 100 Error (%) = {[ (N + 1) × B × 64 × 2 (2×n − 1) When the new bit rate is selectable, the rate will be set in the register after sending ACK in response.
Page 860 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Command H'40 • Command, H'40 (1 byte): Transition to programming/erasing state Response H'06 • Response, H'06 (1 byte): Response to transition to programming/erasing state. The boot program will return ACK when the user MAT and user boot MAT have been erased normally by the transferred erasing program.
Page 861: Table 21.12 Programming/Erasing Commands
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 7. After selection of the device and clock mode, programming/erasing information of the user boot MAT and user MAT should be inquired using the user boot MAT information inquiry (H'24), user MAT information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27).
Page 862: Figure 21.23 Programming Sequence
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Programming: Programming is executed by a programming-selection command and a 128-byte programming command. First, the host should send the programming-selection command, and select the programming method and programming MATs. There are two programming selection commands according to the area and method for programming.
Page 863 Section 21 Flash Memory (0.18-µm F-ZTAT Version) User Boot MAT Programming Selection The boot program will transfer a programming program in response to the user boot MAT programming selection command. The data is programmed to the user boot MAT by the transferred programming program.
Page 864 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Command H'50 Address Data ··· ··· • Command, H'50 (1 byte): 128-byte programming • Programming address (4 bytes): Start address for programming. Multiple of the size specified in response to the programming unit inquiry command. (e.g.
Page 865 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Response H'06 • Response, H'06 (one byte): Response to 128-byte programming. On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR • Error response, H'D0 (1 byte): Error response to 128-byte programming •...
Page 866: Figure 21.24 Erasure Sequence
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Host Boot program Preparation for erasure (H'48) Transfer of erasure program Erasure (Erase-block number) Repeat Erasure Erasure (H'FF) Figure 21.24 Erasure Sequence Erasure Selection The boot program will transfer the erasing program in response to the erasure selection command. User MAT data is erased by the transferred erasing program.
Page 867 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Command H'58 Size Block number • Command, H'58 (1 byte): Erasure • Size (1 byte): The number of characters that represents the erase-block number. Fixed at 1. • Block number (1 byte): Number of the block to be erased •...
Page 868 Section 21 Flash Memory (0.18-µm F-ZTAT Version) (11) Memory Read The boot program will return the data in the specified address in response to the memory read command. Command H'52 Size Area Read address Read size • Command, H'52 (1 byte): Memory read •...
Page 869 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Command H'4A • Command, H'4A (1 byte): Sum check for user boot MAT Response H'5A Size Checksum of MAT • Response, H'5A (1 byte): Response to the checksum of user boot MAT • Size (1 byte): The number of characters that represents the checksum. Fixed at 4.
Page 870 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Error Response H'CC H'52 • Error response, H'CC (1 byte): Error response to blank check for user boot MATs • Error code, H'52 (1 byte): Erasure incomplete error (15) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result in response to the user MAT blank check command.
Page 871: Table 21.13 Status Code
Section 21 Flash Memory (0.18-µm F-ZTAT Version) Table 21.13 Status Code Code Description H'11 Device Selection Wait H'12 Clock Mode Selection Wait H'13 Bit Rate Selection Wait H'1F Programming/Erasing State Transition Wait (Bit rate selection is completed) H'31 Programming/Erasing State H'3F Programming/Erasing Selection Wait (Erasure is completed) H'4F...
Page 872: Usage Notes
Section 21 Flash Memory (0.18-µm F-ZTAT Version) 21.9 Usage Notes 1. The initial state of a Renesas product at shipment is the erased state. For a product whose history of erasing is undefined, automatic erasure for checking the initial state (erased state) and compensating is recommended.
Page 873 Section 21 Flash Memory (0.18-µm F-ZTAT Version) 11. If data other than H'FF (4 bytes) is written to the key code area (in normal mode: H'001E to H'001F, in advance mode: H'00003C to H'00003F) of flash memory, reading cannot be performed in programmer mode.
Page 874 Section 21 Flash Memory (0.18-µm F-ZTAT Version) Rev. 3.00 Jul. 14, 2005 Page 826 of 986 REJ09B0098-0300...
Page 875: Section 22 Boundary Scan (Jtag)
Section 22 Boundary Scan (JTAG) Section 22 Boundary Scan (JTAG) The JTAG (Joint Test Action Group) is standardized as an international standard, IEEE Standard 1149.1, and is open to the public as IEEE Standard Test Access Port and Boundary-Scan Architecture. Although the name of the function is boundary scan and the name of the group who worked on standardization is the JTAG, the JTAG is commonly used as the name of a boundary scan architecture and a serial interface to access the devices having the architecture.
Page 876: Figure 22.1 Jtag Block Diagram
Section 22 Boundary Scan (JTAG) ETCK ETMS controller Decoder ETRST ETDI SDIR SDIDR ETDO [Legend] SDIR: Instruction register SDBPR: Bypass register SDBSR: Boundary scan register SDIDR: ID code register Figure 22.1 JTAG Block Diagram Rev. 3.00 Jul. 14, 2005 Page 828 of 986 REJ09B0098-0300...
Page 877: Input/Output Pins
Section 22 Boundary Scan (JTAG) 22.2 Input/Output Pins Table 22.1 shows the JTAG pin configuration. Table 22.1 Pin Configuration Pin Name Abbreviation Function Test clock ETCK Input Test clock input Provides an independent clock supply to the JTAG. As the clock input to the ETCK pin is supplied directly to the JTAG, a clock waveform with a duty cycle close to 50% should be input.
Page 878: Register Descriptions
Section 22 Boundary Scan (JTAG) 22.3 Register Descriptions The JTAG has the following registers. • Instruction register (SDIR) • Bypass register (SDBPR) • Boundary scan register (SDBSR) • ID code register (SDIDR) Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI).
Page 879 Section 22 Boundary Scan (JTAG) Bit Name Initial Value Description Test Set Bits 0000: EXTEST mode 0001: Setting prohibited 0010: CLAMP mode 0011: HIGHZ mode 0100: SAMPLE/PRELOAD mode 0101: Setting prohibited 1101: Setting prohibited 1110: IDCODE mode (Initial value) 1111: BYPASS mode 27 to 14 ...
Page 880: Bypass Register (Sdbpr)
Section 22 Boundary Scan (JTAG) 22.3.2 Bypass Register (SDBPR) SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 22.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed.
Page 881 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input     Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable...
Page 882 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input     Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable...
Page 883 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input...
Page 884 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input    ...
Page 885 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input     Input     Input     Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input...
Page 886 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input...
Page 887 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input...
Page 888 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input...
Page 889 Section 22 Boundary Scan (JTAG) Pin No. Pin Name Input/Output Bit No. Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output To ETDO Note: The enable signals are active-high.
Page 890: Id Code Register (Sdidr)
Section 22 Boundary Scan (JTAG) 22.3.4 ID Code Register (SDIDR) SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output H'0036200F, which is a fixed code, from ETDO. However, no serial data can be written to SDIDR via ETDI. 31 28 0 0 0 0 0 0 0 0...
Page 891: Jtag Reset
Section 22 Boundary Scan (JTAG) Test-logic-reset Run-test/idle Select-DR-scan Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure 22.2 TAP Controller State Transitions 22.4.2 JTAG Reset The JTAG can be reset in two ways. • The JTAG is reset when the ETRST pin is held at 0. •...
Page 892: Boundary Scan
Section 22 Boundary Scan (JTAG) 22.5 Boundary Scan The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 22.5.1 Supported Instructions This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE).
Page 893 Section 22 Boundary Scan (JTAG) EXTEST Instruction code: B'0000 The EXTEST instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board.
Page 894: Notes
Section 22 Boundary Scan (JTAG) IDCODE Instruction code: B'1110 When the IDCODE instruction is enabled, the value of the ID code register is output from the ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the IDCODE instruction is being executed, the test circuit does not affect the system circuit.
Page 895: Figure 22.3 Reset Signal Circuit Without Reset Signal Interference
Section 22 Boundary Scan (JTAG) Board edge pin This LSI System reset Power-on reset circuit ETRST ETRST Figure 22.3 Reset Signal Circuit without Reset Signal Interference 3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode, IDCODE mode will be entered.
Page 896: Figure 22.4 Serial Data Input/Output (1)
Section 22 Boundary Scan (JTAG) SDIR serial data input/output SDIR is captured into the shift register in Capture-IR, and bits 0 to 31 of SDIR are output in that order from the ETDO pin in Shift-IR. Data input from the ETDI pin is written to SDIR in Update-IR. ETDI ETDI Bit 31...
Page 897: Section 23 Clock Pulse Generator
Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and subclock waveform forming circuit.
Page 898: Oscillator
Section 23 Clock Pulse Generator 23.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 23.1.1 Connecting Crystal Resonator Figure 23.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance R , given in table 23.1 should be used.
Page 899: External Clock Input Method
Section 23 Clock Pulse Generator Table 23.2 Crystal Resonator Parameters Frequency (MHz) (max) (Ω) (max) (pF) 23.1.2 External Clock Input Method Figure 23.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode.
Page 900: Figure 23.5 External Clock Input Timing
Section 23 Clock Pulse Generator Table 23.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item Symbol Unit Test Conditions  External clock input pulse Figure 23.5 width low level  External clock input pulse width high level ...
Page 901: Figure 23.6 Timing Of External Clock Output Stabilization Delay Time
Section 23 Clock Pulse Generator Table 23.4 External Clock Output Stabilization Delay Time Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Item Symbol Unit Remarks  µs External clock output stabilization delay Figure 23.6 DEXT...
Page 902: Duty Correction Circuit
Section 23 Clock Pulse Generator 23.2 Duty Correction Circuit The duty correction circuit generates the system clock (φ) by correcting the duty of the clock output from the oscillator. 23.3 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16, and φ/32 clocks.
Page 903: Subclock Input Circuit
Section 23 Clock Pulse Generator 23.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin. Figure 23.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin. When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the pin to 0.
Page 904: Subclock Waveform Forming Circuit
Section 23 Clock Pulse Generator EXCLH EXCLL × 0.5 EXCL EXCLr EXCLf Figure 23.8 Subclock Input Timing 23.6 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform forming circuit samples the subclock using a divided φ clock. The sampling frequency is set by the NESEL bit in LPWRCR.
Page 905: Handling Of X1 And X2 Pins
Section 23 Clock Pulse Generator 23.8 Handling of X1 and X2 Pins The X1 and X2 pins should be open, as shown in figure 23.9. Open Open Figure 23.9 Handling of X1 and X2 Pins 23.9 Usage Notes 23.9.1 Notes on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference;...
Page 906 Section 23 Clock Pulse Generator Rev. 3.00 Jul. 14, 2005 Page 858 of 986 REJ09B0098-0300...
Page 907: Section 24 Power-Down Modes
Section 24 Power-Down Modes Section 24 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules.
Page 908: Register Descriptions
Section 24 Power-Down Modes 24.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Page 909 Section 24 Power-Down Modes Bit Name Initial Value R/W Description STS2 Standby Timer Select 2 to 0 STS1 On canceling software standby mode, watch mode, or subactive mode, these bits select the wait time for clock STS0 stabilization from clock oscillation start. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency.
Page 910: Low-Power Control Register (Lpwrcr)
Section 24 Power-Down Modes Table 24.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 20 MHz 10 MHz 8 MHz 6 MHz 4 MHz Unit 8192 states 16384 states 32768 states 65536 states 10.9 16.4 131072 states 13.1 16.4 21.8 32.8...
Page 911 Section 24 Power-Down Modes Initial Bit Name Value R/W Description LSON R/W Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled.
Page 912: Module Stop Control Registers H, L, And A (Mstpcrh, Mstpcrl, Mstpcra)
Section 24 Power-Down Modes 24.1.3 Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. •...
Page 913 Section 24 Power-Down Modes • MSTPCRA Bit Name Initial Value R/W Corresponding Module MSTPA7 0 Reserved The initial value should not be changed. MSTPA6 0 Reserved The initial value should not be changed. MSTPA5 0 Reserved The initial value should not be changed. MSTPA4 0 Reserved The initial value should not be changed.
Page 914: Mode Transitions And Lsi States
Section 24 Power-Down Modes MSTPCRB specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. 24.2 Mode Transitions and LSI States Figure 24.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction.
Page 915: Figure 24.1 Mode Transition Diagram
Section 24 Power-Down Modes Program halt state STBY pin = Low Hardware Reset state standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SSBY = 0, LSON = 0 Sleep mode SLEEP instruction (main clock) High-speed mode...
Page 916: Table 24.2 Lsi Internal States In Each Operating Mode
Section 24 Power-Down Modes Table 24.2 LSI Internal States in Each Operating Mode High- Medium- Module Sub- Sub- Software Hardware Function Speed Speed Sleep Stop Watch active sleep Standby Standby System clock pulse Function- Function- Function- Function- Halted Halted Halted Halted Halted generator...
Page 917 Section 24 Power-Down Modes High- Medium- Module Sub- Sub- Software Hardware Function Speed Speed Sleep Stop Watch active sleep Standby Standby Halted (reset) On-chip Function- Function- Function- Function- Halted Halted Halted Halted peripheral ing/Halted (retained) (retained) (retained) (retained) PWMX modules (reset) SCI_1 Halted...
Page 918: Medium-Speed Mode
Section 24 Power-Down Modes 24.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the operating clock can be selected from φ/2, φ/4, φ/8, φ/16, or φ/32. On-chip peripheral modules other than the bus masters and KBU operate on the system clock (φ).
Page 919: Sleep Mode
Section 24 Power-Down Modes Figure 24.2 shows an example of medium-speed mode timing. Medium-speed mode φ , peripheral module clock Bus master clock SBYCR SBYCR Internal address bus Internal write signal Figure 24.2 Medium-Speed Mode Timing 24.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0.
Page 920: Software Standby Mode
Section 24 Power-Down Modes 24.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0.
Page 921: Figure 24.3 Software Standby Mode Application Example
Section 24 Power-Down Modes Figure 24.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin.
Page 922: Hardware Standby Mode
Section 24 Power-Down Modes 24.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained.
Page 923: Watch Mode
Section 24 Power-Down Modes 24.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
Page 924: Subsleep Mode
Section 24 Power-Down Modes 24.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1.
Page 925: Subactive Mode
Section 24 Power-Down Modes 24.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high- speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR both set to 1, and the PSS bit in TCSR (WDT_1) set to 1.
Page 926: Module Stop Mode
Section 24 Power-Down Modes 24.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle.
Page 927: Usage Notes
Section 24 Power-Down Modes 24.12 Usage Notes 24.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, while a high level is output or the pull-up MOS is on, the current consumption is not reduced by the amount of current to support the high level output.
Page 928 Section 24 Power-Down Modes Rev. 3.00 Jul. 14, 2005 Page 880 of 986 REJ09B0098-0300...
Page 929: Section 25 List Of Registers
Section 25 List of Registers Section 25 List of Registers The list of registers gives information on the on-chip I/O register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module.
Page 930 Section 25 List of Registers 5. Register addresses (classification by type of module) • The register addresses are described by modules • The register addresses are described in channel order when the module has multiple channels. Rev. 3.00 Jul. 14, 2005 Page 882 of 986 REJ09B0098-0300...
Page 931: Register Addresses (Address Order)
Section 25 List of Registers 25.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Data Access Number...
Page 932 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits On-chip RAM host base address RAMBARH H'FDEC register H On-chip RAM host base address RAMBARL H'FDED register L Address space set register ASSR H'FDEE On-chip RAM address space set RAMASSR...
Page 933 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Port G noise canceller enable register PGNCE H'FE06 PORT Port G noise canceller mode control PGNCMC H'FE07 PORT register Port G noise cancel cycle setting PGNCCS H'FE08 PORT...
Page 934 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Status register 3 STR3 H'FE32 LPC channel address register H LADR3H H'FE34 LPC channel address register L LADR3L H'FE35 SERIRQ control register 0 SIRQCR0 H'FE36 SERIRQ control register 1...
Page 935 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Port C output data register PCODR H'FE4C PORT Port D output data register PDODR H'FE4D PORT Port C input data register PCPIN H'FE4E PORT (read) Port C data direction register...
Page 936 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Keyboard matrix interrupt mask KMIMR H'FE81 register (RELOCATE = 1) Pull-up MOS control register KMPCR H'FE82 PORT (RELOCATE = 1) Keyboard matrix interrupt mask KMIMRA H'FE83 register A...
Page 937 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Keyboard buffer transmit data KBTR_1 H'FEC3 KBU_1 register_1 Keyboard control register 1_2 KBCR1_2 H'FEC4 KBU_2 Keyboard buffer transmit data KBTR_2 H'FEC5 KBU_2 register_2 Timer XY control register TCR_XY H'FEC6...
Page 938 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Keyboard control register 2_0 KBCR2_0 H'FEDB KBU_0 Keyboard control register H_1 KBCRH_1 H'FEDC KBU_1 Keyboard control register L_1 KBCRL_1 H'FEDD KBU_1 Keyboard data buffer register_1 KBBR_1 H'FEDE KBU_1...
Page 939 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits IRQ sense control register 16 L ISCR16L H'FEFB IRQ sense port select register 16 ISSR16 H'FEFC IRQ sense port select register ISSR H'FEFD Peripheral clock select register PCSR H'FF82...
Page 940 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Output control register B OCRB H'FF94 Timer control register H'FF96 Timer output compare control TOCR H'FF97 register Input capture register A ICRA H'FF98 Output control register AR OCRAR H'FF98...
Page 941 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Timer control/status register_0 TCSR_0 H'FFA8 (read) WDT_0 Timer counter_0 TCNT_0 H'FFA8 (write) WDT_0 Timer counter_0 TCNT_0 H'FFA9 (read) WDT_0 Port A output data register PAODR H'FFAA PORT...
Page 942 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits System control register SYSCR H'FFC4 SYSTEM 8 Mode control register MDCR H'FFC5 SYSTEM 8 Bus control register H'FFC6 Wait state control register WSCR H'FFC7 Timer control register _0 TCR_0...
Page 943 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits A/D data register CH ADDRCH H'FFE4 Converter A/D data register CL ADDRCL H'FFE5 Converter A/D data register DH ADDRDH H'FFE6 Converter A/D data register DL ADDRDL H'FFE7 Converter...
Page 944 Section 25 List of Registers Data Access Number Register Name Abbreviation Address Module Width States of Bits Timer counter_Y TCNT_Y H'FFF4 TMR_Y (RELOCATE = 0) Time constant register C TCORC H'FFF5 TMR_X Timer input select register TISR H'FFF5 TMR_Y (RELOCATE = 0) Time constant register A_X TCORA_X H'FFF6...
Page 945: Register Bits
Section 25 List of Registers 25.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 946 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HBAR1L HB1A23 HB1A22 HB1A21 HB1A20 HB1A19 HB1A18 HB1A17 HB1A16 HBAR2H HB2A31 HB2A30 HB2A29 HB2A28 HB2A27 HB2A26 HB2A25 HB2A24 HBAR2L...
Page 947 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PTCNT1 SCL0AS SCL1AS SCL0BS SCL1BS SDA0AS SDA1AS SDA0BS SDA1BS PORT       PTCNT2 LPCS LDRQS...
Page 948 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SIRQCR1 IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2 IDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ODR1...
Page 949 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TPU_0   TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA...
Page 950 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module   DACR TEST PWME PWMX DADRA DA13 DA12 DA11 DA10  DADRB DA13 DA12 DA11 DA10 REGS DACNT...
Page 951 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SAR_1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 IIC_1 ICCR_1 IEIC ACKE BBSY IRIC ICSR_1 ESTP STOP IRTR AASX...
Page 952 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module       ABRKCR BARA BARB  BARC IER16 IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E...
Page 953 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 TOCR ICRDMS OCRAMS ICRS OCRS OLVLA OLVLB ICRA/ bit15 bit14 bit13...
Page 954 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR PORT P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR...
Page 955 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PWOERB OE15 OE14 OE13 OE12 OE11 OE10 PWDPRB OS15 OS14 OS13 OS12 OS11 OS10   PWSL PWCKE PWCKS...
Page 956 Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module        TCONRS TMRX/Y TMR_X, TMR_Y Notes: 1. In normal mode and Smart Card interface mode, bit names differ in part. ( ) : Bit name in Smart Card interface mode.
Page 957: Register States In Each Operating Mode
Section 25 List of Registers 25.3 Register States in Each Operating Mode High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        TCR_1 Initialized Initialized TPU_1...
Page 958 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        ASSR Initialized Initialized      ...
Page 959 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        PFNOCR Initialized Initialized      ...
Page 960 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module          IDR2      ...
Page 961 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        TCNT_0 Initialized Initialized TPU_0     ...
Page 962 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        TSTR Initialized Initialized      ...
Page 963 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        KBCRL_1 Initialized Initialized KBU_1     ...
Page 964 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        ISSR16 Initialized Initialized      ...
Page 965 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        SMR_2 Initialized Initialized SCI_2     ...
Page 966 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module          P7PIN PORT     ...
Page 967 Section 25 List of Registers High- Speed/ Register Medium- Sub- Sub- Module Software Hardware Abbreviation Reset Speed Watch Sleep Active Sleep Stop Standby Standby Module        ICMR_0 Initialized Initialized IIC_0     ...
Page 968: Register Selection Condition
Section 25 List of Registers 25.4 Register Selection Condition Lower Address Register Abbreviation Register selection condition Module H'FD40 TCR_1 MSTP1 = 0 TPU_1 H'FD41 TMDR_1 H'FD42 TIOR_1 H'FD44 TIER_1 H'FD45 TSR_1 H'FD46 TCNT_1 H'FD48 TGRA_1 H'FD4A TGRB_1 H'FDD4 LADR4H MSTP0 = 0 H'FDD5 LADR4L H'FDD6...
Page 969 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FDF0 SAR1 MSTP0 = 0 H'FDF1 SAR2 H'FDF2 FWPRH H'FDF3 FWPRM H'FDF4 FWPRL H'FDF5 RAMAR H'FDF6 FRPRH H'FDF7 FRPRM H'FDF8 FRPRL H'FDF9 UCMDTR H'FDFA FLWARH H'FDFB FLWARL H'FDFC LMCMIDCR H'FDFD...
Page 970 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FE20 TWR0MW MSTP0 = 0 TWR0SW H'FE21 TWR1 H'FE22 TWR2 H'FE23 TWR3 H'FE24 TWR4 H'FE25 TWR5 H'FE26 TWR6 H'FE27 TWR7 H'FE28 TWR8 H'FE29 TWR9 H'FE2A TWR10 H'FE2B TWR11 H'FE2C TWR12...
Page 971 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FE41 HICR1 MSTP0 = 0 H'FE42 HICR2 H'FE43 HICR3 H'FE44 WUEMRB No condition H'FE45 WUEMR H'FE46 PGODR No condition PORT H'FE47 PGPIN (read) PGDDR (write) H'FE48 PEPCR H'FE49 PFODR H'FE4A...
Page 972 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FE70 TCR_2 MSTP1 = 0 TPU_2 H'FE71 TMDR_2 H'FE72 TIOR_2 H'FE74 TIER_2 H'FE75 TSR_2 H'FE76 TCNT_2 H'FE78 TGRA_2 H'FE7A TGRB_2 H'FE7D SYSCR3 No condition SYSTEM H'FE7E MSTPCRA H'FE81 KMIMR (RELOCATE = 1) MSTP2 = 0...
Page 973 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FEC0 KBCR1_0 MSTP2 = 0 H'FEC1 KBTR_0 H'FEC2 KBCR1_1 H'FEC3 KBTR_1 H'FEC4 KBCR1_2 H'FEC5 KBTR_2 H'FEC6 TCRXY MSTP8 = 0 TMR_XY H'FEC8 TCR_Y (RELOCATE = 1) TMR_Y H'FEC9 TCSR_Y (RELOCATE = 1) H'FECA...
Page 974 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FEE1 KBCRL_2 MSTP2 = 0 H'FEE2 KBBR_2 H'FEE3 KBCR2_2 H'FEE4 KBCOMP No condition IrDA H'FEE6 DDCSWR MSTP4 = 0, IICE in STCR = 1 IIC_0, IIC_1 H'FEE8 ICRA No condition H'FEE9...
Page 975 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FF86 MSTPCRH FLSHE in STCR = 0 SYSTEM H'FF87 MSTPCRL H'FF88 SMR_1 (RELOCATE = 1) MSTP6 = 0 SCI_1 SMR_1 (RELOCATE = 0) MSTP6 = 0, IICE in STCR = 0 ICCR_1 (RELOCATE = 0) MSTP3 = 0, IICE in STCR = 1 IIC_1...
Page 976 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FFA0 SMR_2 (RELOCATE = 1) MSTP5 = 0 SCI_2 SMR_2 (RELOCATE = 0) MSTP5 = 0, IICE in STCR = 0 DADRAH (RELOCATE = 0) MSTP11 = 0, REGS in PWMX MSTPA1 = 0,...
Page 977 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FFB0 P1DDR No condition PORT H'FFB1 P2DDR H'FFB2 P1DR H'FFB3 P2DR H'FFB4 P3DDR H'FFB5 P4DDR H'FFB6 P3DR H'FFB7 P4DR H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBC PBODR H'FFBD...
Page 978 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FFCE TCORB MSTP12 = 0 TMR_0, H'FFCF TCORB_1 TMR_1 H'FFD0 TCNT_0 H'FFD1 TCNT_1 H'FFD2 PWOERB No condition H'FFD4 PWDPRB H'FFD6 PWSL MSTP11 = 0 MSTPA0 = 0 H'FFD7 PWDR 15 to 8 H'FFD8...
Page 979 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FFF1 KMIMR (RELOCATE = 0) MSTP2 = 0, TMRX/Y in TCONRS KINWUE in STCR = 1 TCSR_X (RELOCATE = 1) MSTP8 = 0 TMR_X TCSR_X (RELOCATE = 0) MSTP8 = 0, TMRX/Y in TCONRS KINWUE in SYSCR = 0...
Page 980 Section 25 List of Registers Lower Address Register Abbreviation Register selection condition Module H'FFFC TCONRI (RELOCATE = 1) MSTP8 = 0 TMR_Y TCONRI (RELOCATE = 0) MSTP8 = 0, KINWUE in SYSCR = 0 H'FFFE TCONRS (RELOCATE = 1) MSTP8 = 0 TMR_X, TMR_Y TCONRS (RELOCATE = 0) MSTP8 = 0, KINWUE in SYSCR = 0...
Page 981: Register Addresses (Classification By Type Of Module)
Section 25 List of Registers 25.5 Register Addresses (Classification by Type of Module) Number Data Address Module Register name of bits Address Initial value width states WUEMRB H'FE44 H'FF WUEMR H'FE45 H'FF KMIMR H'FE81 H'BF (RELOCATE = 1) KMIMR H'FFF1 H'BF (RELOCATE = 0) KMIMRA...
Page 982 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states DTCERB H'FEEF H'00 DTCERC H'FEF0 H'00 DTCERD H'FEF1 H'00 DTCERE H'FEF2 H'00 DTVECR H'FEF3 H'00 PORT P1PCR H'FFAC H'00 PORT P1DDR H'FFB0 H'00 PORT P1DR...
Page 983 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states PORT P9DDR H'FFC0 H'00 PORT P9DR H'FFC1 H'00/H'40 PORT PAODR H'FFAA H'00 PORT PAPIN H'FFAB H'00 PORT PADDR H'FFAB H'00 PORT PBODR H'FFBC H'00 ...
Page 984 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states  PORT PGPIN H'FE47 (Read) PORT PGDDR H'FE47 (Write) H'00 PORT PTCNT0 H'FE10 H'00 PORT PTCNT1 H'FE11 H'00 PORT PTCNT2 H'FE12 H'00 PWOERB H'FFD2 H'00...
Page 985 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states PWMX DADRBL H'FEA7 H'FF (RELOCATE = 1) PWMX DADRBL H'FFA7 H'FF (RELOCATE = 0) PWMX PCSR H'FF82 H'00 TIER H'FF90 H'01 TCSR H'FF91 H'00 H'FF92...
Page 986 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states TPU_1 TIOR_1 H'FD42 H'00 TPU_1 TIER_1 H'FD44 H'40 TPU_1 TSR_1 H'FD45 H'C0 TPU_1 TCNT_1 H'FD46 H'0000 TPU_1 TGRA_1 H'FD48 H'FFFF TPU_1 TGRB_1 H'FD4A H'FFFF TPU_2...
Page 987 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states TMR_X TCORC H'FFF5 H'FF TMR_X TCORA_X H'FFF6 H'FF TMR_X TCORB_X H'FFF7 H'FF TMR_X TCONRI H'FFFC H'00 TMR_Y TCR_Y H'FEC8 H'00 (RELOCATE = 1) TMR_Y TCR_Y H'FFF0...
Page 988 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states WDT_1 TCSR_1 H'FFEA (Write) H'00 WDT_1 TCSR_1 H'FFEA (Read) H'00 WDT_1 TCNT_1 H'FFEA (Write) H'00 WDT_1 TCNT_1 H'FFEB (Read) H'00 IrDA KBCOMP H'FEE4 H'00 SCI_1...
Page 989 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states IIC_1 SAR_1 H'FECF H'00 (RELOCATE = 1) IIC_1 ICCR_1 H'FED0 H'01 (RELOCATE = 1) IIC_1 ICSR_1 H'FED1 H'00 (RELOCATE = 1) IIC_1 ICXR_1 H'FED5 H'00...
Page 990 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states KBU_2 KBCRH_2 H'FEE0 H'70 KBU_2 KBCRL_2 H'FEE1 H'70 KBU_2 KBBR_2 H'FEE2 H'00 KBU_2 KBCR2_2 H'FEE3 H'F0 RBUFAR H'FDE0 H'EF EBLKR H'FDE1 H'00 LMCST1 H'FDE2 H'00...
Page 991 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states LMCMIDCR H'FDFC H'00 LMCDIDCR H'FDFD H'00  TWR0MW H'FE20  TWR0SW H'FE20  TWR1 H'FE21  TWR2 H'FE22  TWR3 H'FE23  TWR4 H'FE24 ...
Page 992 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states STR2 H'FE3E H'00 HISEL H'FE3F H'03 HICR0 H'FE40 H'00 HICR1 H'FE41 H'00  HICR2 H'FE42  HICR3 H'FE43 LADR4H H'FDD4 H'00 LADR4L H'FDD5 H'00 ...
Page 993 Section 25 List of Registers Number Data Address Module Register name of bits Address Initial value width states FPCS H'FEA9 H'00 FECS H'FEAA H'00 FKEY H'FEAC H'00  FMATS H'FEAD FTDAR H'FEAE H'00 SYSTEM MSTPCRA H'FE7E H'00 SYSTEM SBYCR H'FF84 H'01 SYSTEM LPWRCR...
Page 994 Section 25 List of Registers Rev. 3.00 Jul. 14, 2005 Page 946 of 986 REJ09B0098-0300...
Page 995: Section 26 Electrical Characteristics
Section 26 Electrical Characteristics Section 26 Electrical Characteristics 26.1 Absolute Maximum Ratings Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* –0.3 to +4.3 Input voltage (except port 7, A, G, P97, –0.3 to V +0.3 P86, P52, and P42)
Page 996: Dc Characteristics
Section 26 Electrical Characteristics 26.2 DC Characteristics Table 26.2 lists the DC characteristics. Table 26.3 lists the permissible output currents. Table 26.4 lists the bus drive characteristics. Table 26.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV...
Page 997 Section 26 Electrical Characteristics Test Item Symbol Min. Typ. Max. Unit Conditions RES, STBY, MD2, MD1,  Input low –0.3 × 0.1 MD0, FWE, and ETRST voltage  NMI, EXTAL, and input pins other –0.3 × 0.2 than (1) and (3) above ...
Page 998: Table 26.2 Dc Characteristics (2)
Section 26 Electrical Characteristics Table 26.2 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV = 0 V Item Symbol Min. Typ. Max. Unit Test Conditions I ...
Page 999: Table 26.2 Dc Characteristics (3) Using Lpc Function
Section 26 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connection to the power supply (V ).
Page 1000: Table 26.3 Permissible Output Currents
Section 26 Electrical Characteristics Table 26.3 Permissible Output Currents Conditions: V = 3.0 V to 3.6 V, V = 0V Item Symbol Min. Typ. Max. Unit   Permissible output SCL0, SDA0, SCL1, SDA1, low current (per pin) ExSCLA, ExSDAA, ExSCLB, ExSDAB, PS2AC to PS2CC, PS2AD to PS2CD, and...

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H8s/2100 series H8s/2114r R4f2114r

Renesas H8S Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 Data Transfer Controller (DTC)

Section 8 I/O Ports

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