11.4
Operation
11.4.1
Pulse Output
Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference.
When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and
OLVLB bits are inverted by software.
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
FRC
Figure 11.2 Example of Pulse Output
Section 11 16-Bit Free-Running Timer (FRT)
Counter clear
Rev. 3.00 Jul. 14, 2005 Page 289 of 986
REJ09B0098-0300