Renesas H8S Series Hardware Manual page 742

Section 18 LPC Interface (LPC)
2. ID read command
When receiving the CMD0 or CMD1 address in an LPC/FW memory read cycle, the LPC
sends back an MID/DID. Byte and word transfers are supported by the ID read command. In
word transfer, an MID is sent back before a DID. In longword transfer, the SYNC field is not
sent back.
3. Status read command
When receiving the CMD2 or CMD3 address in an LPC/FW memory read cycle, the slave
sends back an LMCST1/LMCST2. Byte and word transfers are supported by the status read
command. In word transfer, an LMCST1 is sent back before an LMCST2. In longword
transfer, the SYNC field is not sent back.
4. Clear Status command
When receiving the CMD4 address in an LPC/FW memory write cycle, the slave clears the
FLPERR, FLEERR, and ERASEE bits.
5. Erasing enable command
When receiving the CMD5 address in an LPC/FW memory write cycle, the slave sets the
ERASEE bit. Setting the ERASEE bit allows to receive the block erasure command.
6. Block erasure command
When receiving the CMD6 address and a block number data with ERASEE = 1 in an LPC/FW
memory write cycle, the LPC performs a block erasure. The LPC stores the erase block
number in EBLKR, sets the FLEI interrupt flag (one of the LMCI interrupt sources) and clears
the ERASEE bit when receiving the block erasure command. The LPC must clear the FLEI
flag to 0 after reading FLEI = 1. The host reads LMCST1, waiting for the FLEI bit cleared.
After reading FLEI = 0 and checking the FLERR bit, the host starts the next command. During
block erasure, the commands for a memory access or an interrupt generation are prohibited.
7. Write enable command
When receiving the CMD7 address in an LPC/FW memory write cycle, the LPC sets the
WRITEE bit. Setting the WRITEE bit allows to receive the data write (on-chip RAM)
command.
8. Data write (on-chip RAM) command
When receiving an RM address and the data write command with WRITEE = 1 in an LPC/FW
memory write cycle, the LPC writes data of the address in the on-chip RAM. Byte, word, and
longword transfers are supported in FW memory write cycles. Since receiving the data write
command to the on-chip RAM generates a memory access, confirm the LMCBUSY bit cleared
to 0 after completion of an LPC/FW memory write cycle. It is needed to decide the internal
memory access status since a wait state is not inserted in a write cycle. When the LMCBUSY
is set, the commands for a memory access or an interrupt generation are prohibited. The
WRITEE bit is not cleared after the data write command is completed. To clear the WRITEE
bit, the WRITEE clear command must be executed.
Rev. 3.00 Jul. 14, 2005 Page 694 of 986
REJ09B0098-0300