Smi, Hirq1, Hirq6, Hirq9, Hirq10, Hirq11, And Hirq12 - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)
18.5.2

SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12

The LPC interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can
be requested from LPC channel 2, 3, or 4.
There are two ways of clearing a host interrupt request.
When the IEDIR bit in SIRQCR0is cleared to 0, host interrupt sources and LPC channels are all
linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of
ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt
enable bit is automatically cleared to 0, and the host interrupt request is cleared.
When the IEDIR bit is set to 1 in SIRQCR0, a host interrupt is requested by the only upon the host
interrupt enable bits. The host interrupt enable bit is not cleared when OBF is cleared. Therefore,
SMIE1, SMIE2, SMIE3A and SMIE3B, SMIE, IRQ10En, and IRQ11En lose their respective
functional differences. In order to clear a host interrupt request, it is necessary to clear the host
interrupt enable bit. (n = 2 to 4.)
Table 18.13 summarizes the methods of setting and clearing these bits, and figure 18.17 shows the
processing flowchart.
Rev. 3.00 Jul. 14, 2005 Page 711 of 986
REJ09B0098-0300