Operation; Lpc Interface Activation; Lpc I/O Cycles - Renesas H8S Series Hardware Manual

18.4

Operation

18.4.1

LPC interface Activation

The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in
HICR0, LPC4E in HICR4, or LMCCR1 in LMCE. When the LPC interface is activated, the
related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins.
In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports
(P81, P80, PB0, and PB1) to the LPC interface's input/output pins.
Use the following procedure to activate the LPC interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
the LPC module is initialized internally.
2. When using channel 4, set LADR4 to determine the I/O address
3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data
registers are to be used.
Set the relevant registers when the LPC/FW memory cycle is used.
4. Set the enable bit (LPC4E to LPC1E, and LMCE) for the channel to be used.
5. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be
used.
6. Set the selection bits for other functions (SDWNE, IEDIR).
7. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF, FLPI, FLEI, BUFINI
and USERI). Read IDR or TWR15 to clear IBF.
8. Set receive complete interrupt enable bits (IBFIE4 to IBFIE1, ERRIE, FLPIE, FLEIE,
BUFINIE, and USERIE) as necessary.
18.4.2

LPC I/O Cycles

There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O
write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O
read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this
LSI supports I/O read, I/O write, LPC memory read, LPC memory write, FW memory read, and
FW memory write cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 677 of 986
REJ09B0098-0300