Dtc Mode Register B (Mrb); Dtc Source Address Register (Sar) - Renesas H8S Series Hardware Manual

7.2.2

DTC Mode Register B (MRB)

MRB selects the DTC operating mode.
Bit Bit Name Initial Value
7 CHNE Undefined
6 DISEL Undefined
5 to 0 — All undefined
7.2.3

DTC Source Address Register (SAR)

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
R/W Description
— DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, see section 7.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of data transfers,
clearing of the interrupt source flag, and clearing of
DTCER are not performed.
— DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends. (DTC does not
clear the interrupt source flag which is as an activation
source, to 0.) When this bit is cleared to 0, a CPU
interrupt request is generated only when the specified
number of data transfers ends. (DTC does not clear the
interrupt source flag which is as an activation source, to
0.)
— Reserved
These bits have no effect on DTC operation. The write
value should always be 0.
Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Jul. 14, 2005 Page 139 of 986
REJ09B0098-0300