Subactive Mode - Renesas H8S Series Hardware Manual
16-bit single-chip microcomputer
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- Hardware manual (1047 pages) ,
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Section 24 Power-Down Modes
24.9
Subactive Mode
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR both
set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode with
the LSON bit in LPWRCR set to 1, a direct transition is made to subactive mode. Similarly, if an
interrupt occurs in subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU operates at a low speed based on the subclock and sequentially
executes programs. On-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and
WDT_1 are also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must all be
cleared to 0.
Subactive mode is cleared by the SLEEP instruction, RES pin input, or STBY pin input.
When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in
LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, subactive mode is cleared and
a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in
SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set
to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the
SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR set to 1, the LSON bit in LPWRCR
cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed
mode.
For details on direct transitions, see section 24.11, Direct Transitions.
When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with
the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the
RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after
the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev. 3.00 Jul. 14, 2005 Page 877 of 986
REJ09B0098-0300
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