Reso Signal Output Timing; Figure 14.4 Ovf Flag Set Timing; Figure 14.5 Output Timing Of Reso Signal - Renesas H8S Series Hardware Manual

Section 14 Watchdog Timer (WDT)
φ
TCNT
Overflow signal
(internal signal)
OVF

RESO Signal Output Timing

14.4.3
When TCNT overflows in watchdog timer mode, the OVF flag in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 14.5.
φ
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
Rev. 3.00 Jul. 14, 2005 Page 422 of 986
REJ09B0098-0300
H'FF

Figure 14.4 OVF Flag Set Timing

H'FF

Figure 14.5 Output Timing of RESO signal

H'00
H'00
132 states
518 states