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Renesas H8S/2100 Series Hardware Manual

16-bit single-chip microcomputer

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REJ09B0452-0100

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All information contained in this material, including products and product

specifications at the time of publication of this material, is subject to change by

Renesas Technology Corp. without notice. Please review the latest information

published by Renesas Technology Corp. through various means, including the

Renesas Technology Corp. website (http://www.renesas.com).

Rev.1.00

Revision Date: Apr. 28, 2008

H8S/2117R

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2100 Series

Hardware Manual

H8S/2117R

Group

R4F2117R

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Page 1 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Rev. 1.00 Apr. 28, 2008 Page ii of xxvi...
Page 3 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 4 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 5 Manual Application Note Examples of applications and The latest versions are available from our sample programs web site. Renesas Technical Preliminary report on the Update specifications of a product, document, etc. Rev. 1.00 Apr. 28, 2008 Page v of xxvi...
Page 6 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name"...
Page 7 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Table of Bits] Bit Name Initial Value R/W...
Page 8 4. Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description Bus controller Clock pulse generator Interrupt controller Serial communication interface 8-bit timer 16-bit timer pulse unit Watchdog timer • Abbreviations other than those listed above Abbreviation Description ACIA...
Page 9: Table Of Contents
Contents Section 1 Overview....................1 Features..........................1 1.1.1 Applications......................1 1.1.2 Overview of Functions....................2 List of Products ........................7 Block Diagram ........................8 Pin Descriptions ........................9 1.4.1 Pin Assignments ....................... 9 1.4.2 Pin Assignment in Each Operating Mode............... 12 1.4.3 Pin Functions ......................
Page 10 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)....58 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn..58 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32........58 2.7.6 Immediate#xx:8, #xx:16, or #xx:32..............59 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) ........59 2.7.8 Memory Indirect@@aa:8 ...................
Page 11 Section 5 Interrupt Controller ................85 Features..........................85 Input/Output Pins ......................... 87 Register Descriptions ......................88 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) ..........89 5.3.2 Address Break Control Register (ABRKCR) ............91 5.3.3 Break Address Registers A to C (BARA to BARC)..........92 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)....
Page 12 Section 6 Bus Controller (BSC) ................ 133 Register Descriptions......................133 6.1.1 Bus Control Register (BCR) ................. 133 6.1.2 Wait State Control Register (WSCR) ..............134 Section 7 I/O Ports..................... 135 Register Descriptions......................143 7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) ....144 7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9)............
Page 13 7.3.2 Port Control Register 1 (PTCNT1) ............... 195 7.3.3 Port Control Register 2 (PTCNT2) ............... 196 Section 8 8-Bit PWM Timer (PWMU)..............197 Features..........................197 Input/Output Pins ....................... 199 Register Descriptions ......................200 8.3.1 PWM Control Register A (PWMCONA) ............. 202 8.3.2 PWM Control Register B (PWMCONB)..............
Page 14 10.3.4 Timer Interrupt Enable Register (TIER)............... 258 10.3.5 Timer Status Register (TSR)................. 260 10.3.6 Timer Counter (TCNT)..................263 10.3.7 Timer General Register (TGR) ................263 10.3.8 Timer Start Register (TSTR) ................263 10.3.9 Timer Synchro Register (TSYR) ................264 10.4 Interface to Bus Master...................... 265 10.4.1 16-Bit Registers ....................
Page 15 Section 11 16-Bit Cycle Measurement Timer (TCM) ........305 11.1 Features..........................305 11.2 Input/Output Pins ....................... 307 11.3 Register Descriptions ......................307 11.3.1 TCM Timer Counter (TCMCNT) ................. 309 11.3.2 TCM Cycle Upper Limit Register (TCMMLCM) ..........309 11.3.3 TCM Cycle Lower Limit Register (TCMMINCM)..........310 11.3.4 TCM Input Capture Register (TCMICR)..............
Page 16 12.3.9 TDP Control Register 1 (TDPCR1)..............338 12.3.10 TDP Control Register 2 (TDPCR2)..............340 12.3.11 TDP Interrupt Enable Register (TDPIER) ............341 12.4 Operation ........................... 343 12.4.1 Timer Mode ......................343 12.4.2 Cycle Measurement Mode ..................345 12.5 Interrupt Sources........................ 350 12.6 Usage Notes ........................
Page 17 13.5.6 Timing of Overflow Flag (OVF) Setting .............. 379 13.6 TMR_0 and TMR_1 Cascaded Connection ............... 380 13.6.1 16-Bit Count Mode ....................380 13.6.2 Compare-Match Count Mode ................380 13.7 TMR_Y and TMR_X Cascaded Connection ..............381 13.7.1 16-Bit Count Mode ....................381 13.7.2 Compare-Match Count Mode ................
Page 18 Section 15 Serial Communication Interface (SCI)..........403 15.1 Features..........................403 15.2 Input/Output Pins....................... 405 15.3 Register Descriptions......................406 15.3.1 Receive Shift Register (RSR) ................407 15.3.2 Receive Data Register (RDR)................407 15.3.3 Transmit Data Register (TDR)................407 15.3.4 Transmit Shift Register (TSR) ................407 15.3.5 Serial Mode Register (SMR) ................
Page 19 15.7.8 Clock Output Control.................... 458 15.8 Interrupt Sources........................ 460 15.8.1 Interrupts in Normal Serial Communication Interface Mode ....... 460 15.8.2 Interrupts in Smart Card Interface Mode .............. 461 15.9 Usage Notes ........................462 15.9.1 Module Stop Mode Setting ................... 462 15.9.2 Break Detection and Processing ................
Page 20 16.4.4 Switching between System Clock and Sub Clock ..........487 16.5 Noise Canceler Circuit....................... 488 16.6 Reset Conditions ........................ 490 16.7 Interrupt Sources........................ 490 16.8 Usage Note......................... 491 Section 17 Serial Communication Interface with FIFO (SCIF)......493 17.1 Features..........................493 17.2 Input/Output Pins.......................
Page 21 18.3.3 Second Slave Address Register (SARX) .............. 538 18.3.4 I C Bus Mode Register (ICMR)................540 18.3.5 I C Bus Control Register (ICCR)................543 18.3.6 I C Bus Status Register (ICSR)................551 18.3.7 I C Bus Control Initialization Register (ICRES)........... 555 18.3.8 I C Bus Extended Control Register (ICXR)............
Page 22 19.4.10 First KCLK Falling Interrupt................609 19.5 Usage Notes ........................613 19.5.1 KBIOE Setting and KCLK Falling Edge Detection ..........613 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission ....614 19.5.3 Module Stop Mode Setting ................... 614 19.5.4 Medium-Speed Mode ...................
Page 23 20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ............. 674 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15......675 20.6 Usage Note......................... 678 20.6.1 Data Conflict......................678 Section 21 FSI Interface ..................681 21.1 Features..........................
Page 24 21.6 Interrupt Sources........................ 725 21.7 Usage Note......................... 725 21.7.1 Longword Transfer in FW Memory Write Cycles..........725 Section 22 A/D Converter ................. 727 22.1 Features..........................727 22.2 Input/Output Pins....................... 729 22.3 Register Descriptions......................730 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ..........731 22.3.2 A/D Control/Status Register (ADCSR) ..............
Page 25 24.8.1 Boot Mode ......................776 24.8.2 User Program Mode....................780 24.8.3 User Boot Mode....................789 24.8.4 Storable Areas for On-Chip Program and Program Data........793 24.9 Protection ........................... 798 24.9.1 Hardware Protection ..................... 798 24.9.2 Software Protection....................799 24.9.3 Error Protection..................... 799 24.10 Switching between User MAT and User Boot MAT ............
Page 26 Section 27 List of Registers................855 27.1 Register Addresses (Address Order).................. 856 27.2 Register Bits........................878 27.3 Register States in Each Operating Mode ................896 27.4 Register Selection Condition ..................... 912 27.5 Register Addresses (Classification by Type of Module) ........... 934 Section 28 Electrical Characteristics ..............
Page 27: Section 1 Overview
The core of each product in the H8S/2117R Group of CISC (complex instruction set computer) microcomputers is an H8S/2600 CPU, which has an internal 16-bit architecture. The H8S/2600 CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcomputers; H8/300, H8/300H, and H8S.
Page 28: Overview Of Functions
Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of this LSI in outline. Table 1.1 Overview of Functions Module/ Classification Function Description • Memory ROM lineup: Flash memory version H8S/2117R: 160 Kbytes • RAM capacity: 8 Kbytes •...
Page 29 Section 1 Overview Module/ Classification Function Description Mode 2: Single-chip mode operating (selected by driving the MD2 and MD0 pins low and MD1 mode pin high) Mode 4: Boot mode (selected by driving the MD2 high and MD1 and MD0 pins low) Mode 6: On-chip emulation mode (selected by driving the MD2 and MD1 pins high and the...
Page 30 Section 1 Overview Module/ Classification Function Description • 8-bit timers A/B × six channels Timer 8-bit PWM • timer Selectable from four clock sources (PWMU) • Cycle selectable for each channel • Supports 8-bit single pulse mode, 16-bit single pulse mode, and 8-bit pulse division mode.
Page 31 Section 1 Overview Module/ Classification Function Description • 8 bits × four channels (also works as 16 bits × two channels) Timer 8-bit timer • (TMR) Selectable from seven clocks: six internal clocks and one external clock • Pulse output or PWM output with an arbitrary duty cycle •...
Page 32 Section 1 Overview Module/ Classification Function Description • One channel High- • Supports communications between this LCI and SPI flash performance interface memory communication (FSI) • Capable of operating as a master • Supports LPC reset and LPC shut-down • One channel •...
Page 33: List Of Products
Indicates the product-specific number. H8S/2117R Indicates the type of ROM device. Indicates the product classification Microcomputer R indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Name Code Rev. 1.00 Apr. 28, 2008 Page 7 of 994 REJ09B0452-0100...
Page 34: Block Diagram
Section 1 Overview Block Diagram H8S/2600CPU Clock pulse generator XTAL EXTAL (1 channel) (flasf memory) ETRST PJ0* 16-bit TCM PJ1* (4 channels) PJ2* (1 channel) PJ3* PJ4* P30/LAD0 PJ5* P31/LAD1 PJ6* P32/LAD2 PJ7* SCIF P33/LAD3 16-bit TDP P34/LFRAME (1 channel) (3 channels) PI0* P35/LRESET...
Page 35: Pin Descriptions
Section 1 Overview Pin Descriptions 1.4.1 Pin Assignments 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 FSISS/PB7/RTS AVSS FSICK/PB6/CTS...
Page 36 Section 1 Overview AVref AVCC AVref AVCC AVSS AVSS H8S/2117R Group PLBG0176GA-A BP-176V (Top View) PE3* XTAL EXTAL PE4* PE1* ETRST PE2* INDEX : Non-connection pin (with solder ball) Note: * Not supported by the system development tool (emulator) Figure 1.4 Pin Assignments (BP-176V) Rev.
Page 37 Section 1 Overview AVCC AVref AVSS H8S/2117R Group PTLG0145JB-A (Top View) ETRST XTAL EXTAL INDEX : NC Pin Note: Not supported by the systen development tool (emulator) Figure 1.5 Pin Assignments (TLP-145V) Rev. 1.00 Apr. 28, 2008 Page 11 of 994 REJ09B0452-0100...
Page 38: Pin Assignment In Each Operating Mode
Section 1 Overview 1.4.2 Pin Assignment in Each Operating Mode Table 1.3 H8S/2117R Group Pin Assignment in Each Operating Mode Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) P43/TMI1/SCK2/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWX0/PWMU4B/TCMCYI3 P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3 ...
Page 39 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) P92/IRQ0 P91/IRQ1 P90/IRQ2   K3 (N) PH2/CIRI   L3 (N) ETRST 28 (T) L2 (T) K4 (T) PE4*/ETMS PE3*/ETDO 30 (T) M1 (T) K2 (T) PE2*/ETDI...
Page 40 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) PF5/PWMU3A PF4/PWMU2A PF3/IRQ11/TMOX/TDPCKI0/TDPMCI0 PF2/IRQ10/TMOY/TDPCYI0 PF1/IRQ9/PWMU1A PF0/IRQ8/PWMU0A   N7 (N) 51 (N) R7 (N) L6 (N) PG7/ExIRQ15/ExSCLB 52 (N) P7 (N) M7 (N) PG6/ExIRQ14/ExSDAB 53 (N) M8 (N)
Page 41 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0)   P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC     AVCC AVref    AVref P60/KIN0 P61/KIN1 P62/KIN2 P63/KIN3 P64/KIN4...
Page 42 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) PC2/TIOCC0/TCLKA/WUE10 PC1/TIOCB0/WUE9 PC0/TIOCA0/WUE8           PB7/RTS/FSISS PB6/CTS/FSICK PB5/DTR/FSIDI Rev. 1.00 Apr. 28, 2008 Page 16 of 994 REJ09B0452-0100...
Page 43 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) PB4/DSR/FSIDO PB3/DCD/PWMU1B PB2/RI/PWMU0B   PB1/LSCI PB0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK   P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 135 (N) B6 (N)
Page 44 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0)   XTAL EXTAL Notes: (N) in Pin No. indicates the pin is driven by NMOS push-pull/open drain and has 5 V input tolerance.
Page 45: Pin Functions
Section 1 Overview 1.4.3 Pin Functions Table 1.4 Pin Functions Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function Power 1, 36, 86 A1, J15, B1, M1, Input Power supply pins. Connect all supply P1, P2 these pins to the system power supply.
Page 46 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function Interrupts Input Nonmaskable interrupt request input IRQ15 to G2, H2, F1, G4, Input These pins request a maskable IRQ0 19 to 21, J4, J3, H4, G1, interrupt.
Page 47 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function 16-bit timer TCLKA Input Timer external clock input pins pulse unit TCLKB (TPU) TCLKC TCLKD TIOCA0 Input/ Input capture input/output TIOCB0 Output compare output/PWM output TIOCC0 pins for TGRA_0 to TGRD_0 TIOCD0 TIOCA1...
Page 48 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function 14-bit PWM PWX0 Output PWM timer pulse output pins timer PWX1 (PWMX) Serial TxD1 Output Transmit data output pins communi- TxD2 cation RxD1 Input Receive data input pins interface RxD2 (SCI_1,...
Page 49 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function Serial FTxD Output Transmit data output pin communi- FRxD Input Receive data input pin cation Input Ring indicator input pin interface with FIFO Input Data carrier detect input pin (SCIF) Input Data set ready input pin...
Page 50 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function FSISS Output FSI slave select pin interface FSICK Output Clock output pin (FSI) FSIDI Input Receive data input pin FSIDO Output Transmit data output pin CIRI Input Receive data input pin interface (CIR)
Page 51 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function C bus SCL0 Input/ C clock I/O pins. The output interface SCL1 Output type is NMOS open-drain. (IIC) SCL2 To which pin the clock is ExSCLA input or output can be ExSCLB selected from the SCL0, SCL1, ExSCLA, and...
Page 52 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function I/O port P77 to 75 to 68 P15, N13, L12, N13, Input 8-bit input pins R15, P14, M13, N12, R14, P13, N11, L10, R13, N12 M11, N10 P86 to 135 to 129 B6, A6, C6, C6, B5,...
Page 53 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function I/O port PH5 to 142 to 140, B3, D4, C4, B3, A4, Input/ 6-bit input/output pins 26, 12, 10 C4, K2, F3, J2, F2, E2 Output PI7 to PI0  ...
Page 54 Section 1 Overview Rev. 1.00 Apr. 28, 2008 Page 28 of 994 REJ09B0452-0100...
Page 55: Section 2 Cpu
Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU.
Page 56: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
Section 2 CPU  16 ÷ 8-bit register-register divide: 12 states  16 × 16-bit register-register multiply: 3 states  32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes  Normal mode*  Advanced mode • Power-down state ...
Page 57: Differences From H8/300 Cpu
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added.
Page 58: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU.
Page 59 Section 2 CPU H'0000 Exception vector 1 H'0001 H'0002 Exception vector 2 H'0003 H'0004 Exception vector 3 H'0005 Exception H'0006 Exception vector 4 vector table H'0007 H'0008 Exception vector 5 H'0009 H'000A Exception vector 6 H'000B Figure 2.1 Exception Vector Table (Normal Mode) EXR* (16 bits) Reserved*...
Page 60: Advanced Mode
Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access to a 16-Mbyte maximum address space is provided. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers.
Page 61 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address.
Page 62: Address Space
Section 2 CPU Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 63: Registers
Section 2 CPU Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
Page 64: General Registers
Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 65: Program Counter (Pc)
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Page 66: Condition-Code Register (Ccr)
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 67: Multiply-Accumulate Register (Mac)
Section 2 CPU Initial Bit Name Value Description Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
Page 68: Data Formats
Section 2 CPU Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 69 Section 2 CPU Data Type Register Number Data Format Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 70: Memory Data Formats
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.
Page 71: Instruction Set
Section 2 CPU Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L 5 POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L 23...
Page 72: Table Of Instructions Classified By Function
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register)
Page 73 Section 2 CPU Symbol Description :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Data Transfer Instructions Instruction Size*...
Page 74 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.
Page 75 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 76 Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 77 Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 78 Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ∼...
Page 79 Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function  Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 80 Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function  TRAPA Starts trap-instruction exception handling.  Returns from an exception-handling routine.  SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves general register or memory contents or immediate data to CCR or EXR.
Page 81 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function  if R4L ≠ 0 then EEPMOV.B Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next;  if R4 ≠ 0 then EEPMOV.W Repeat @ER5+ → @ER6+ R4–1 →...
Page 82: Basic Instruction Formats
Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats.
Page 83: Addressing Modes And Effective Address Calculation
Section 2 CPU Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 84: Register Indirect With Displacement@(D:16, Ern) Or @(D:32, Ern)
Section 2 CPU 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand.
Page 85: Immediate#Xx:8, #Xx:16, Or #Xx:32
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode* Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24)
Page 86: Memory Indirect@@Aa:8
Section 2 CPU 2.7.8 Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
Page 87: Effective Address Calculation
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation...
Page 88 Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Note: * Normal mode is not available in this LSI. Rev.
Page 89: Processing States
Section 2 CPU Processing States The H8S/2600 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 90 Section 2 CPU Program execution state SLEEP instruction with SLEEP LSON = 0 and instruction SSBY = 0 with LSON = 0, PSS = 0, and SSBY = 1 Request for exception End of handling exception handling Sleep mode Interrupt request Exception-handling state Software standby mode...
Page 91: Usage Note
Section 2 CPU Usage Note 2.9.1 Notes on Using the Bit Operation Instruction Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits.
Page 92 Section 2 CPU Rev. 1.00 Apr. 28, 2008 Page 66 of 994 REJ09B0452-0100...
Page 93: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Operating Mode Selection This LSI supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection.
Page 94: Register Descriptions
Section 3 MCU Operating Modes Register Descriptions The following registers are related to the operating modes. Table 3.2 Register Configuration Data Bus Register Name Abbreviation Initial Value Address Width  Mode control register MDCR H'FFC5 System control register SYSCR H'09 H'FFC4 Serial timer control register STCR...
Page 95: System Control Register (Syscr)
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space.
Page 96 Section 3 MCU Operating Modes Initial Bit Name Value Description KINWUE Keyboard Control Register Access Enable When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMR), pull- up MOS control register (KMPCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC,...
Page 97: Serial Timer Control Register (Stcr)
Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Initial Bit Name Value Description IICX2 C Transfer Rate Select 2 to 0 IICX1 These bits control the IIC operation.
Page 98 Section 3 MCU Operating Modes Initial Bit Name Value Description FLSHE Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), power-down state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (PCSR).
Page 99: System Control Register 3 (Syscr3)
Section 3 MCU Operating Modes 3.2.4 System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Initial Bit Name Value Description — Reserved The initial value should not be changed. EIVS* Extended interrupt Vector Select* Selects compatible mode or extended mode for the interrupt vector table.
Page 100: Address Map
Section 3 MCU Operating Modes Address Map Figures 3.1 shows the address map in each operating mode. Mode 2 (EXPE = 0) Advanced mode Single-chip mode ROM: 160 Kbytes RAM: 8 Kbytes H'000000 On-chip ROM 160 Kbytes H'027FFF H'028000 Reserved area H'0FFFFF H'FF0000 Reserved area...
Page 101: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, illegal instruction, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 102: Exception Sources And Exception Vector Table
Section 4 Exception Handling Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the exception sources and their vector addresses. The EIVS bit in the system control register 3 (SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended vector mode.
Page 103 Section 4 Exception Handling Vector Addresses Vector Exception Source Number Advanced Mode Internal interrupt* H'000060 to H'000063   H'000074 to H'000077 Reserved for system use H'000078 to H'00007B Reserved for system use H'00007C to H'00007F Reserved for system use H'000080 to H'000083 H'000084 to H'000087 External interrupt WUE15 to WUE8...
Page 104 Section 4 Exception Handling Table 4.3 Exception Handling Vector Table (Extended Vector Mode) Vector Addresses Vector Exception Source Number Advanced Mode Reset H'000000 to H'000003 Reserved for system use H'000004 to H'000007  H'00000C to H'00000F Illegal instruction H'000010 to H'000013 Reserved for system use H'000014 to H'000017 Direct transition...
Page 105: Reset
Section 4 Exception Handling Vector Addresses Vector Exception Source Number Normal Mode Internal interrupt* H'000088 to H'00008B   H'0000DC to H'0000DF External interrupt IRQ8 H'0000E0 to H'0000E3 IRQ9 H'0000E4 to H'0000E7 IRQ10 H'0000E8 to H'0000EB IRQ11 H'0000EC to H'0000EF IRQ12 H'0000F0 to H'0000F3 IRQ13...
Page 106: Interrupts Immediately After Reset
Section 4 Exception Handling Figure 4.1 shows an example of the reset sequence. Vector Internal Prefetch of first fetch processing program instruction φ Internal address bus (1) U (1) L Internal read signal Internal write signal High Internal data bus (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L)
Page 107: Interrupt Exception Handling
Section 4 Exception Handling Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE8) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority.
Page 108: Exception Handling By Illegal Instruction
Section 4 Exception Handling Exception Handling by Illegal Instruction The exception handling by the illegal instruction starts when an undefined code is executed. The exception handling by the illegal instruction is always executable in the program execution state. The exception handling operates as follows: 1.
Page 109: Stack Status After Exception Handling
Section 4 Exception Handling Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Advanced mode Normal mode CCR* (16 bits) (24 bits) Notes: * Ignored on return. Normal mode is not available in this LSI. Figure 4.2 Stack Status after Exception Handling Rev.
Page 110: Usage Note
Section 4 Exception Handling Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even.
Page 111: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Features • Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks.
Page 112 Section 5 Interrupt Controller EIVS SYSCR3 INTM1, INTM0 SYSCR NMIEG NMI input NMI input Interrupt request IRQ input IRQ input Vector number Priority level ISCR determination KMIMR WUEMR I, UI KIN input KIN, WUE WUE input input Internal interrupt sources WOVI0 to IBFI3 Interrupt controller [Legend]...
Page 113: Input/Output Pins
Section 5 Interrupt Controller Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Pin Name Function Input Nonmaskable external interrupt pin Rising edge or falling edge can be selected IRQ15 to IRQ0, Input Maskable external interrupt pins ExIRQ15 to ExIRQ6 Rising-edge, falling-edge, or both-edge detection, or level- sensing, can be selected individually for each pin.
Page 114: Register Descriptions
Section 5 Interrupt Controller Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, System Control Register 3 (SYSCR3). Table 5.2 Register Configuration Data Bus...
Page 115: Interrupt Control Registers A To D (Icra To Icrd)
Section 5 Interrupt Controller Data Bus Register Name Abbreviation Initial Value Address Width Wake-up sense control register WUESCR H'00 H'FE84 Wake-up input interrupt status WUESR H'00 H'FE85 register Wake-up enable register H'00 H'FE86 1. Address in the upper cell: when RELOCATE = 0, address in the lower cell: when Note: RELOCATE = 1 2.
Page 116 Section 5 Interrupt Controller Table 5.3 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0) Register Bit Name ICRA ICRB ICRC ICRD ICRn7 IRQ0 A/D converter SCIF IRQ8 to IRQ11 ICRn6 IRQ1 TCM_0, TCM_1, SCI_1 IRQ12 to IRQ15 TCM_2, TCM_3 ICRn5...
Page 117: Address Break Control Register (Abrkcr)
Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested. Bit Name Initial Value R/W Description Undefined Condition Match Flag Address break source flag.
Page 118: Break Address Registers A To C (Bara To Barc)
Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. •...
Page 119: Irq Sense Control Registers (Iscr16H, Iscr16L, Iscrh, Iscrl)
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6. • ISCR16H Bit Name Initial Value R/W Description IRQ15SCB IRQn Sense Control B...
Page 120 Section 5 Interrupt Controller • ISCR16L Bit Name Initial Value Description IRQ11SCB IRQn Sense Control B IRQ11SCA IRQn Sense Control A IRQ10SCB 00: Interrupt request generated at low level of IRQn IRQ10SCA or ExIRQn input IRQ9SCB 01: Interrupt request generated at falling edge of IRQ9SCA IRQn or ExIRQn input IRQ8SCB...
Page 121 Section 5 Interrupt Controller • ISCRL Bit Name Initial Value Description IRQ3SCB IRQn Sense Control B IRQ3SCA IRQn Sense Control A IRQ2SCB 00: Interrupt request generated at low level of IRQn IRQ2SCA input IRQ1SCB 01: Interrupt request generated at falling edge of IRQ1SCA IRQn input IRQ0SCB...
Page 122: Irq Enable Registers (Ier16, Ier)
Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. • IER16 Bit Name Initial Value Description IRQ15E IRQn Enable IRQ14E The IRQn interrupt request is enabled when this bit is 1.
Page 123: Irq Status Registers (Isr16, Isr)
Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. • ISR16 Bit Name Initial Value Description IRQ15F R/(W)* [Setting condition] IRQ14F R/(W)* When the interrupt source selected by the ISCR16 registers occurs IRQ13F R/(W)*...
Page 124 Section 5 Interrupt Controller • ISR Bit Name Initial Value Description IRQ7F R/(W)* [Setting condition] IRQ6F R/(W)* When the interrupt source selected by the ISCR registers occurs IRQ5F R/(W)* [Clearing conditions] IRQ4F R/(W)* • When writing 0 to IRQnF flag after reading IRQ3F R/(W)* IRQnF = 1...
Page 125: Keyboard Matrix Interrupt Mask Registers (Kmimra Kmimr) Wake-Up Event Interrupt Mask Registers (Wuemr)
Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE8). •...
Page 126 Section 5 Interrupt Controller • WUEMR Bit Name Initial Value Description WUEMR15 Wake-Up Event Interrupt Mask WUEMR14 These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). WUEMR13 0: Enables a wake-up event input interrupt request WUEMR12 1: Disables a wake-up event input interrupt request WUEMR11...
Page 127 Section 5 Interrupt Controller Figure 5.2 shows the relation between the IRQ7 and IRQ6 interrupts, KMIMR, and KMIMRA in H8S/2140B Group compatible vector mode. The relation in extended vector mode is shown in figure 5.3. KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) IRQ6 internal...
Page 128 Section 5 Interrupt Controller In H8S/2140B Group compatible vector mode, interrupt input from the IRQ7 pin is ignored when even one of the KMIMR15 to KMIMR8 bits is cleared to 0. If the KIN7 to KIN0 pins or KIN15 to KIN8 pins are specified to be used as key-sensing interrupt input pins and wake-up event interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing.
Page 129: Irq Sense Port Select Register 16 (Issr16) Irq Sense Port Select Register (Issr)
Section 5 Interrupt Controller 5.3.8 IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from the IRQ15 to IRQ7 pins and ExIRQ15 to ExIRQ7 pins. •...
Page 130: Wake-Up Sense Control Register (Wuescr) Wake-Up Input Interrupt Status Register (Wuesr) Wake-Up Enable Register (Wer)
Section 5 Interrupt Controller 5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt Status Register (WUESR) Wake-Up Enable Register (WER) WUESCR selects the interrupt source of the wake-up event interrupt inputs (WUE15 to WUE8). WUESR is an interrupt request flag register. WER enables/disables interrupts. •...
Page 131: Interrupt Sources
Section 5 Interrupt Controller • WER Bit Name Initial Value Description WUEE WUE Enable The WUE interrupt request is enabled when this bit| is 1. 0: Wake-up input interrupt request is disabled 1: Wake-up input interrupt request is enabled 6 to 0  All 0 Reserved The initial values should not be changed.
Page 132 Section 5 Interrupt Controller When the interrupts are requested while IRQ15 to IRQ0 interrupt requests are generated at low level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling starts. Then put the relevant IRQ input back to high level within the interrupt handling routine and clear the IRQnF bit (n = 15 to 0) in ISR to 0.
Page 133 Section 5 Interrupt Controller  When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8 bits must all be set to 1. If even one of these bits is cleared to 0, the IRQ7 interrupt input from the IRQ7 pin is ignored.
Page 134: Internal Interrupt Sources
Section 5 Interrupt Controller 5.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller.
Page 135 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority — Reserved for system use H'000060 — High WDT_0 WOVI0 (Interval timer) H'000064 ICRA1 WDT_1 WOVI1 (Interval timer) H'000068 ICRA0 — Address break H'00006C —...
Page 136 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority TCM_2 TICI2 (Input capture) H'0000C8 ICRB6 High TCMI2 (Compare match) TOVMI2 (Cycle overflow) TUDI2 (Cycle underflow) TOVI2 (Overflow) TCM_3 TICI3 (Input capture) H'0000CC TCMI3 (Compare match) TOVMI3 (Cycle overflow) TUDI3 (Cycle underflow) TOVI3 (Overflow)
Page 137 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority TMR_0 CMIA0 (Compare match A) H'000100 ICRB3 High CMIB0 (Compare match B) H'000104 OVI0 (Overflow) H'000108 — Reserved for system use H'00010C — TMR_1 CMIA1 (Compare match A) H'000110 ICRB2...
Page 138 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority KBIA (Reception completion A) H'000180 ICRB0 High KBIB (Reception completion B) H'000184 KBIC (Reception completion C) H'000188 KBTIA (Transmission completion A)/ H'00018C KBCA (1st KCLKA) KBTIB (Transmission completion B)/ H'000190 KBCB (1st KCLKB)
Page 139 Section 5 Interrupt Controller Table 5.6 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) Origin of Vector Address Interrupt Vector Source Number Name Advanced Mode Priority External pin H'00001C — High IRQ0 H'000040 ICRA7 IRQ1 H'000044 ICRA6 IRQ2 H'000048 ICRA5 IRQ3...
Page 140 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority TPU_2 TGI2A (TGR2A input H'0000AC ICRD1 High capture/compare match) TGI2B (TGR2B input H'0000B0 capture/compare match) TGI2V (Overflow 1) H'0000B4 TGI2U (Underflow 2) H'0000B8 — Reserved for system use H'0000BC —...
Page 141 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority TDP_2 TICI2 (Input capture) H'0000D8 ICRB5 High TCMI2 (Compare match) TPDMXI2 (Cycle overflow) TPDMNI2 (Cycle underflow) TWDMNI2 (Pulse width lower limit underflow) TWDMXI2 (Pulse width upper limit overflow) TOVI2 (Overflow) —...
Page 142 Section 5 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority SCI_2 ERI2 (Reception error) H'000160 ICRC5 High RXI2 (Reception completion) H'000164 TXI2 (Transmission data empty 2) H'000168 TEI2 (Transmission end 2) H'00016C IIC_0 IICI0 (1-byte transmission/reception H'000170 ICRC4 completion)
Page 143: Interrupt Control Modes And Interrupt Operation
Section 5 Interrupt Controller Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state. The interrupt control mode is selected by SYSCR.
Page 144 Section 5 Interrupt Controller Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.8 shows the interrupts selected in each interrupt control mode.
Page 145: Interrupt Control Mode 0
Section 5 Interrupt Controller Table 5.9 shows operations and control signal functions in each interrupt control mode. Table 5.9 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control Setting 3-Level Control Interrupt Default Priority Control Mode INTM1 INTM0 Determination Ο...
Page 146 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Hold pending An interrupt with interrupt...
Page 147: Interrupt Control Mode 1
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. •...
Page 148 Section 5 Interrupt Controller Figure 5.9 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Page 149 Section 5 Interrupt Controller Program execution state Interrupt generated? Hold pending An interrupt with interrupt control level 1? IRQ0 IRQ0 IRQ1 IRQ1 IBFI3 IBFI3 I = 0 I = 0 UI = 0 Save PC and CCR 1, UI Read vector address Branch to interrupt handling routine Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev.
Page 150: Interrupt Exception Handling Sequence
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Page 151: Interrupt Response Times
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.10 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.10 Interrupt Response Times Execution Status Advanced Mode Interrupt priority determination* Number of wait states until executing instruction...
Page 152: Address Breaks
Section 5 Interrupt Controller Address Breaks 5.7.1 Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed.
Page 153: Operation
Section 5 Interrupt Controller 5.7.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority.
Page 154 Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal Vector Internal Instruction fetch fetch fetch fetch fetch operation fetch operation fetch Stack save φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318...
Page 155: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 156: Instructions For Disabling Interrupts
Section 5 Interrupt Controller 5.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 157: External Interrupt Pin In Software Standby Mode And Watch Mode
Section 5 Interrupt Controller 5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode • When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ6, KIN15 to KIN0, and WUE15 to WUE8) are used as external input pins in software standby mode or watch mode, the pins should not be left floating.
Page 158 Section 5 Interrupt Controller Rev. 1.00 Apr. 28, 2008 Page 132 of 994 REJ09B0452-0100...
Page 159: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. Register Descriptions The bus controller has the following registers.
Page 160: Wait State Control Register (Wscr)
Section 6 Bus Controller (BSC) 6.1.2 Wait State Control Register (WSCR) Initial Bit Name Value Description 7, 6 — All 1 Reserved The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed.
Page 161: Section 7 I/O Ports
Section 7 I/O Ports Section 7 I/O Ports Table 7.1 lists the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port input data register (PIN) used to read the pin states.
Page 162 Section 7 I/O Ports Table 7.1 Port Functions Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler    Port 1 General I/O port   ...
Page 163 Section 7 I/O Ports Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler    Port 4 General I/O TCMCKI3/ PWX1/PWMU5B port also TCMMCI3 functioning as TCMCYI3 PWX0/PWMU4B PWMX and...
Page 164 Section 7 I/O Ports Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler      Port 7 General input P77/AN7 port also   P76/AN6 functioning as ...
Page 165 Section 7 I/O Ports Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler KIN15     Port A General I/O PA7/PS2CD port also KIN14  PA6/PS2CC functioning as KIN13...
Page 166 Section 7 I/O Ports Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler   Port D General I/O AN15 port also  AN14 functioning as  A/D converter AN13 analog input...
Page 167 Section 7 I/O Ports Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler PG7/ExSCLB ExIRQ15    Port G General I/O port also PG6/ExSDAB ExIRQ14  functioning as PG5/ExSCLA ExIRQ13 ...
Page 168 Section 7 I/O Ports Function LED Drive Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Bit I/O Input Output Function Current) Canceler     Port J General I/O PJ7* port   PJ6*  ...
Page 169: Register Descriptions
Section 7 I/O Ports Register Descriptions Table 7.2 lists each port registers. Table 7.2 Register Configuration in Each Port Registers Number Port of Pins DDR PCR KMPCR ODR NCE NCMC NCCS NOCR       Port 1 ...
Page 170: Data Direction Register (Pnddr) (N = 1 To 6, 8, 9, A To D, And F To J)
Section 7 I/O Ports 7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) DDR specifies the port input or output for each bit. The upper five bits in P5DDR, the upper one bit in P8DDR, and the upper two bits in PHDDR are reserved.
Page 171: Data Register (Pndr) (N = 1 To 6, 8, And 9)
Section 7 I/O Ports 7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9) DR is a register that stores output data of the pins to be used as the general output port. Since the P96DR bit is determined by the state of the P96 pin, the initial value is undefined. The upper five bits in P5DR and the upper one bit in P8DR are reserved.
Page 172: Pull-Up Mos Control Register (Pnpcr) (N = 1 To 3, 9, B To D, F, H, And J) Pull-Up Mos Control Register (Kmpcr) (Port 6)
Section 7 I/O Ports 7.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 9, B to D, F, H, and J) Pull-Up MOS Control Register (KMPCR) (Port 6) PCR is a register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in the input state, the input pull-up MOS corresponding to the bit in PCR is turned on.
Page 173 Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (1) • Port 1 to 3, 6, 9, and J Port Pin State Reset Software Standby Mode Other Operation Port 1 Port output Port input On/Off Port 2 Port output Port input On/Off Port 3...
Page 174 Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (2) • Port B to D, F, and H Port Pin State Reset Software Standby Mode Other Operation Port B Port output Port input On/Off Port C Port output Port input On/Off Port D Port output...
Page 175: Output Data Register (Pnodr) (N = A To D And F To J)
Section 7 I/O Ports Output Data Register (PnODR) (n = A to D and F to J) 7.1.5 ODR is a register that stores output data for ports. The upper two bits in PHODR are reserved. Bit Name Initial Value Description Pn7ODR ODR stores the output data for the pins that are...
Page 176: Noise Canceler Decision Control Register (Pnncmc) (N = 6, C, And G)
Section 7 I/O Ports Noise Canceler Decision Control Register (PnNCMC) (n = 6, C, and G) 7.1.7 NCMC controls whether 1 or 0 is expected for the input signal to port n pins in bit units. Bit Name Initial Value Description Pn7NCMC 1 expected: 1 is stored in the port data register...
Page 177 Section 7 I/O Ports φ/2, φ/32, φ/8192, φ/16384, φ/32768, φ/65536, φ/131072, φ/262144 Sampling clock selection Latch Latch Latch Latch input Port data register Interrupt input Keyboard input Sampling clock Figure 7.1 Noise Cancel Circuit P6n input PCn input PGn input 1 expected P6n input PCn input...
Page 178: Port Nch-Od Control Register (Pnnocr) (N = C, D, And F To J)
Section 7 I/O Ports Port Nch-OD Control Register (PnNOCR) (n = C, D, and F to J) 7.1.9 The individual bits of NOCR specify output driver type for the pins of port n that is specified as output. The upper two bits in PHNOCR are reserved. Bit Name Initial Value Description...
Page 179: Pin Functions
Section 7 I/O Ports 7.1.10 Pin Functions The pin function is switched according to the setting of the PORTS bit in PTCNT2. (Ports B to D, F, and H) PORTS = 0  NOCR N-ch. driver P-ch. driver Input pull-up Pin function Input pin Output pin...
Page 180: Output Buffer Control
Section 7 I/O Ports Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by “_OE”. This (for example: TIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0).
Page 181: Port 3
Section 7 I/O Ports 7.2.3 Port 3 P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 and LPC3E to LPC1E bits in HICR0 of the LPC, and the P3nDDR bit.
Page 182 Section 7 I/O Ports P46/PWX0/PWMU4B/TCMCYI3 The pin function is switched as shown below according to the combination of the PWMX and PWMU and the P46DDR bit. Setting PWMX PWMU I/O Port Module Name Pin Function PWX0_OE PWMU4B_OE P46DDR   PWMX PWX0 output PWMU...
Page 183 Section 7 I/O Ports P44/TMO1/PWMU2B/TCMCYI2 The pin function is switched as shown below according to the combination of the TMR and PWMU and the P44DDR bit. Setting PWMU I/O Port Module Name Pin Function TMO1_OE PWMU2B_OE P44DDR   TMO1 output PWMU PWMU2B output I/O port...
Page 184 Section 7 I/O Ports P42/SDA1/TCMCYI1 The pin function is switched as shown below according to the combination of the IIC1AS and IIC1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P42DDR bit. When the TCMIPE bit in TCMIER_1 of TCM_1 is set to 1, TCMCYI1 functions as an input pin. Setting IIC_1 I/O Port...
Page 185: Port 5
Section 7 I/O Ports P40/TMI0/TxD2/TCMCYI0 The pin function is switched as shown below according to the combination of the TMR and the SCI and the P40DDR bit. Setting I/O Port Module Name Pin Function TxD2_OE P40DDR  TxD2 output I/O port P40 output P40 input (initial setting)
Page 186 Section 7 I/O Ports P51/FRxD The pin function is switched as shown below according to the SCIFOE1 bit in SCIFCR of the SCIF and the SCIFE bit in HICR5 of the SCIF, and the P51DDR bit. SCIFENABLE = 1: SCIFOE1 + SCIFE Setting Logical Expression I/O Port...
Page 187: Port 6
Section 7 I/O Ports 7.2.6 Port 6 P67/KIN7/IRQ7 When the KMIM7 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN7 input pin. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin.
Page 188: Port 7
Section 7 I/O Ports P65/KIN5, P64/KIN4, P63/KIN3, P62/KIN2, P61/KIN1, P60/KIN0 When the KMIMn bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KINn input pin. The pin function is switched as shown below according to the state of the P6nDDR bit. Setting I/O Port Module...
Page 189: Port 8
Section 7 I/O Ports 7.2.8 Port 8 P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, CKE0 and CKE1 bits in SCR, IIC1AS and IIC1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P86DDR bit.
Page 190 Section 7 I/O Ports P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the register setting of the SCI and the P84DDR bit. Setting I/O Port Module Name Pin Function TxD1_OE P84DDR  TxD1 output I/O port P84 output P84 input...
Page 191 Section 7 I/O Ports P82/CLKRUN The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E bits in HICR0, and the P82DDR bit.
Page 192: Port 9
Section 7 I/O Ports P80/PME The pin function is switched as shown below according to the combination of the register setting of the LPC and the P80DDR bit. Setting I/O Port Module PME_OE Name Pin Function P80DDR PME output  I/O port P80 output P80 input...
Page 193 Section 7 I/O Ports P96/φ/EXCL The pin function is switched as shown below according to the combination of the register settings of the EXCLS bit in PTCNT0, EXCLE bit in LPWRCR, and the P96DDR bit. Setting I/O Port Module Name Pin Function P96DDR φ...
Page 194: Port A
Section 7 I/O Ports 7.2.10 Port A PA7/KIN15/PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN12/PS2BC, PA3/KIN11/PS2AD, PA2/KIN10/PS2AC, PA1/KIN9/PS2DD, PA0/KIN8/PS2DC The pin function is switched according to the combination of the register setting of PS2 and the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KINm input pin.
Page 195: Port B
Section 7 I/O Ports 7.2.11 Port B PB7/RTS/FSISS The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1 of FSI and the PB7DDR bit. Setting SCIF I/O Port Module...
Page 196 Section 7 I/O Ports PB5/DTR/FSIDI The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1of FSI and the PB5DDR bit. Setting SCIF I/O Port Module DTR_OE Name Pin Function...
Page 197 Section 7 I/O Ports PB3/DCD/PWMU1B The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PB3DDR bit. Setting PWMU I/O Port Module Name Pin Function PWMU1B_OE PB3DDR PWMU PWMU1B output I/O port PB3 output ...
Page 198 Section 7 I/O Ports PB1/LSCI The pin function is switched as shown below according to the combination of the register setting of the LPC and the PB1DDR bit. Setting I/O Port Module Name Pin Function LSCI_OE PB1DDR  LSCI output I/O port PB1 output PB1 input...
Page 199: Port C
Section 7 I/O Ports 7.2.12 Port C PC7/WUE15/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC7DDR bit. When the WUEMR15 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE15 input pin.
Page 200 Section 7 I/O Ports PC5/WUE13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC5DDR bit. When the WUEMR13 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE13 input pin. This pin functions as TCLKC input when TPSC2 to TPSC0 in TCR_0 or TCR_2 is set to B'110 or when channel 2 is set to phase counting mode.
Page 201 Section 7 I/O Ports PC3/WUE11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC3DDR bit. When the WUEMR11 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE11 input pin. This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2 are set to B'101 or when channel 1 is set to phase counting mode.
Page 202 Section 7 I/O Ports PC1/WUE9/TIOCB0 The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC1DDR bit. When the WUEMR9 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE9 input pin. This pin functions as TIOCB0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOB3 to IOB0 in TIORH_0 are set to B'10xx.
Page 203: Port D
Section 7 I/O Ports 7.2.13 Port D PD7/AN15, PD6/AN14, PD5/AN13, PD4/AN12, PD3/AN11, PD2/AN10, PD1/AN9, PD0/AN8 The pin function is switched as shown below according to the state of the PDnDDR bit. When this pin is used as an analog input pin, do not set the pin as output. Setting I/O Port Module...
Page 204: Port F
Section 7 I/O Ports PE0/ExEXCL The pin function is switched as shown below according to the combination of the EXCLS bit in PTCNT0 and EXCLE bit in LPWRCR. When the EXCLS bit in PTCNT0 and EXCLE bit in LPWRCR are set to 1, this pin can be used as the ExEXCL input pin. Setting I/O Port Module...
Page 205 Section 7 I/O Ports PF3/TMOX/IRQ11/TDPCKI0/TDPMCI0 The pin function is switched as shown below according to the combination of the register setting of the TMR and the PF3DDR bit. When the PMMS bit in TDPCR2_0 of TDP0 is set to 1, this pin can be used as the TDPMCI0 input pin.
Page 206 Section 7 I/O Ports PF1/IRQ9/PWMU1A The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PF1DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin.
Page 207: Port G
Section 7 I/O Ports 7.2.16 Port G PG7/ExSCLB/ExIRQ15 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG7DDR bit. When the ISS15 bit in ISSR16 is set to 1 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin.
Page 208 Section 7 I/O Ports PG5/ExSCLA/ExIRQ13 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin.
Page 209 Section 7 I/O Ports PG3/SCL2/ExIRQ11 The pin function is switched as shown below according to the combination of the register setting of the IIC and the PG3DDR bit. When the ISS11 bit in ISSR16 is set to 1 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin.
Page 210 Section 7 I/O Ports PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1 The pin function is switched as shown below according to the state of the PG1DDR bit. When the PMMS bit in TDPCR2_1 of the TDP is set to 1, this pin is used as the TDPMCI1 input pin. When the external clock is selected by the CKS2 to CKS0 bits in TDPCR1_1 of the TDP, this pin is used as the TDPCKI1 input pin.
Page 211: Port H
Section 7 I/O Ports 7.2.17 Port H PH5, PH4, PH3 The pin function is switched as shown below according to the state of the PHnDDR bit. Setting I/O Port Module Name Pin Function PHnDDR I/O port PHn output PHn input (initial setting) (n = 5 to 3) PH2/CIRI...
Page 212 Section 7 I/O Ports PH1/ExIRQ7/TDPCKI2/TDPMCI2 The pin function is switched as shown below according to the state of the PH1DDR bit. When the PMMS bit in TDPCR2_2 of the TDP is set to 1, this pin is used as the TDPMCI2 input pin. When the external clock is selected by the CKS2 to CKS0 bits in TDPCR1_2 of the TDP, this pin is used as the TDPCKI2 input pin.
Page 213: Port I
Section 7 I/O Ports 7.2.18 Port I PI7, PI6, PI5, PI4, PI3, PI2, PI1, PI0 The pin function is switched as shown below according to the state of the PInDDR bit. Setting I/O Port Module Name Pin Function PInDDR I/O port PIn output PIn input (initial setting)
Page 214 Section 7 I/O Ports Table 7.4 Available Output Signals and Settings in Each Port Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Internal Module Settings P17_OE P16_OE P15_OE P14_OE P13_OE P12_OE P11_OE P10_OE P27_OE P26_OE P25_OE P24_OE P23_OE P22_OE...
Page 215 Section 7 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Internal Module Settings PWX1_OE PWX1 PWMX.DACR.OEB = 1 PWMU5B_OE PWMU5B PWMU_B.PWMCONB.PWM5E = 1 PWX0_OE PWX0 PWMX.DACR.OEA = 1 PWMU4B_OE PWMU4B PWMU_B.PWMCONB.PWM4E = 1 PWMU3B_OE PWMU3B PWMU_B.PWMCONB.PWM3E = 1 TMO1_OE...
Page 216 Section 7 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Internal Module Settings SCK1_OE SCK1 SCI_1.SMR.C/A = 1 or SCI_1.SMR.C/A = 0, SCR.CKE[1:0] = 01/10/11 SCL1_OE SCL1 PTCNT1.IIC1AS ICE•IIC1AS•IIC1BS = 1 PTCNT1.IIC1BS P85_OE TxD1_OE TxD1 SCI_1.SCR.TE = 1 P83_OE...
Page 217 Section 7 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Internal Module Settings RTS_OE LPC.HICR5.SCIFE, SCIFCR.SCIFOE1, SCIFOE0 SCIFOE = 1: (SCIFE • SCIFOE1 • SCIFOE0 + SCIFE • SCIFOE0) FSISS_OE FSISS FSI.FSICR1.FSIE = 1 FSICK_OE FSICK FSI.FSICR1.FSIE = 1...
Page 218 Section 7 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Internal Module Settings PD7_OE PD6_OE PD5_OE PD4_OE PD3_OE PD2_OE PD1_OE PD0_OE PWMU5A_OE PWMU5A PWMU_A.PWMCONB.PWM5E = 1 PWMU4A_OE PWMU4A PWMU_A.PWMCONB.PWM4E = 1 PWMU3A_OE PWMU3A PWMU_A.PWMCONB.PWM3E = 1 PWMU2A_OE PWMU2A PWMU_A.PWMCONB.PWM2E = 1...
Page 219 Section 7 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Internal Module Settings PI7_OE PI6_OE PI5_OE PI4_OE PI3_OE PI2_OE PI1_OE PI0_OE PJ7_OE PJ6_OE PJ5_OE PJ4_OE PJ3_OE PJ2_OE PJ1_OE PJ0_OE Rev. 1.00 Apr. 28, 2008 Page 193 of 994 REJ09B0452-0100...
Page 220: Change Of Peripheral Function Pins
Section 7 I/O Ports Change of Peripheral Function Pins For the external sub-clock input and IIC input/output, the multi-function I/O ports can be changed. I/O ports that also function as the external interrupt pins are changed by the setting of ISSR16 and ISSR.
Page 221: Port Control Register 1 (Ptcnt1)
Section 7 I/O Ports 7.3.2 Port Control Register 1 (PTCNT1) PTCNT1 selects ports that also function as IIC input/output pins. Bit Name Initial Value Description IIC1BS These bits select input/output pins for IIC_1 IIC1AS IIC1BS IIC1AS Selects P86/SCL1 and P42/SDA1 Selects PG5/ExSCLA and PG4/ExSDAA Selects PG7/ExSCLB and...
Page 222: Port Control Register 2 (Ptcnt2)
Section 7 I/O Ports 7.3.3 Port Control Register 2 (PTCNT2) PTCNT2 selects ports that also function as SCI input/output pins and controls the port specification. Bit Name Initial Value R/W Description  Reserved The initial value should not be changed. TxD2RS 0: TxD2 direct output 1: TxD2 inverted output...
Page 223: Section 8 8-Bit Pwm Timer (Pwmu)
Section 8 8-Bit PWM Timer (PWMU) Section 8 8-Bit PWM Timer (PWMU) This LSI has two channels of 8-bit PWM timers, A and B (PWMU_A and PWMU_B). Each PWMU outputs 6 PWM waveforms. Each of the PWM channels of a PWMU can operate independently.
Page 224 Section 8 8-Bit PWM Timer (PWMU) Figure 8.1 shows a block diagram of the PWMU. Module φ data bus φ/2 Clock φ/4 selection φ/8 Clock generator Transfer control circuit Controller PWMCONA PWMCONB PWMCONC PWMCOND PWM counter/comparator PWMUO PWME [Legend] PWMPRE: PWM prescaler register PWMCONA: PWM control register A for clock control...
Page 225: Input/Output Pins
Section 8 8-Bit PWM Timer (PWMU) Input/Output Pins Table 8.1 shows the PWMU pin configuration. Table 8.1 Pin Configuration Channel Pin Name Function Channel A PWMU0A Output PWM pulse output (8-bit single pulse, 8-bit pulse division) PWMU1A Output PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) PWMU2A...
Page 226: Register Descriptions
Section 8 8-Bit PWM Timer (PWMU) Register Descriptions The PWMU has the following registers. Table 8.2 Register Configuration Data Initial Channel Register Name Abbreviation Value Address Width Channel A PWM control register A_A (for clock control) PWMCONA_A R/W H'00 H'FD0C PWM control register B_A (for output control) PWMCONB_A R/W...
Page 227 Section 8 8-Bit PWM Timer (PWMU) Data Initial Channel Register Name Abbreviation Value Address Width Channel B PWM control register A_B (for clock control) PWMCONA_B R/W H'00 H'FD1C PWM control register B_B (for output control) PWMCONB_B R/W H'00 H'FD1D PWM control register C_B (for mode control) PWMCONC_B R/W H'00...
Page 228: Pwm Control Register A (Pwmcona)
Section 8 8-Bit PWM Timer (PWMU) 8.3.1 PWM Control Register A (PWMCONA) PWMCONA selects the PWM clock source. Initial Bit Name Value Description 7, 6 CLK1, CLK0 All 0 Clock Select 1, 0 These bits select the PWM count clock source. CLK1 CLK0 0: Internal clock φ...
Page 229 Section 8 8-Bit PWM Timer (PWMU) Initial Bit Name Value Description PWM4E PWMU4 Output Enable • 8-bit single-pulse/pulse-division mode 0: PWMU4 output and counter operation are disabled. 1: PWMU4 output and counter operation are enabled. • 16-bit single-pulse mode 0: PWMU4 output and counter operation are disabled.
Page 230 Section 8 8-Bit PWM Timer (PWMU) Initial Bit Name Value Description PWM0E PWMU0 Output Enable • 8-bit single-pulse/pulse division mode 0: PWMU0 output and counter operation are disabled. 1: PWMU0 output and counter operation are enabled. • 16-bit single-pulse mode 0: PWMU0 output and counter operation are disabled.
Page 231: Pwm Control Register C (Pwmconc)
Section 8 8-Bit PWM Timer (PWMU) 8.3.3 PWM Control Register C (PWMCONC) PWMCONC selects the PWM count mode and operating mode for each channel. Initial Bit Name Value Description  Reserved The initial value should not be changed. CNTMD01 Channels 0 and 1 Counter Select 0: Channels 0 and 1 are in 8-bit counter operation.
Page 232: Pwm Control Register D (Pwmcond)
Section 8 8-Bit PWM Timer (PWMU) 8.3.4 PWM Control Register D (PWMCOND) PWMCOND selects the PWM count mode and output phase for each channel. Initial Bit Name Value Description PH5S Channel 5 Output Phase Select 0: PWMU5 direct output 1: PWMU5 inverted output PH4S Channel 4 Output Phase Select 0: PWMU4 direct output...
Page 233: Pwm Prescaler Registers 0 To 5 (Pwmpre0 To Pwmpre5)
Section 8 8-Bit PWM Timer (PWMU) 8.3.5 PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5) PWMPRE are 8-bit readable/writable registers used to set the PWM cycle. The initial value is H'00. When the PWMPRE value is n, the PWM cycle is calculated as follows. 8-Bit Single Pulse Mode PWM cycle = [255 ×...
Page 234 Section 8 8-Bit PWM Timer (PWMU) 16-Bit Single Pulse Mode When 16-bit single pulse mode is selected, PWMPRE0, PWMPRE2, and PWMPRE4 are valid. The settings of PWMPRE1, PWMPRE3, and PWMPRE5 are invalid. PWM cycle = [65535 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255) Table 8.4 Resolution, PWM Conversion Period, and Carrier Frequency (16-Bit Counter Operation) when φ...
Page 235: Pwm Duty Setting Registers 0 To 5 (Pwmreg0 To Pwmreg5)
Section 8 8-Bit PWM Timer (PWMU) 8.3.6 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5) PWMREG0 to PWMREG5 are 8-bit readable/writable registers used to set the high period (duty) of the PWM output pulse. The initial value is H'00. 8-Bit Single Pulse Mode Directly set the high period of the pulse for PWM output.
Page 236: Operation
Section 8 8-Bit PWM Timer (PWMU) Operation The PWMU operates in 8-bit single pulse mode, 16-bit single pulse mode, or 8-bit division pulse mode. 8.4.1 Single-Pulse Mode (8 Bits, 16 Bits) Figure 8.2 shows a block diagram of 8-bit single pulse mode. Figure 8.3 shows a block diagram of 16-bit single pulse mode.
Page 237 Section 8 8-Bit PWM Timer (PWMU) Clock PRELAT0 CNT0 generator Comparator 0 PWMU00 (Output disabled) REGLAT0 PRELAT1 CNT1 Comparator 1 PWMU01 REGLAT1 Figure 8.3 Block Diagram of 16-bit Single Pulse Mode Rev. 1.00 Apr. 28, 2008 Page 211 of 994 REJ09B0452-0100...
Page 238 Section 8 8-Bit PWM Timer (PWMU) When the PWMnE bit (n = 0 to 5) in PWMCONB is set to 1, the PWMU outputs pulses that start with a high level. The updated PWMREG value is written in REGLAT, and the updated PWMPRE value is written in PRELAT.
Page 239 Section 8 8-Bit PWM Timer (PWMU) If the PWMREG value is changed during PWM output, the PWMREG value is loaded into REGLAT when the duty counter overflows (at the beginning of the next PWM cycle). The following shows the PWMU output waveform when the PWMREG value is changed. Duty counter H'FF REGLAT'...
Page 240: Pulse Division Mode
Section 8 8-Bit PWM Timer (PWMU) 8.4.2 Pulse Division Mode In pulse division mode, the higher-order four bits in PWMREG specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The following shows the duty cycle of the basic pulse.
Page 241 Section 8 8-Bit PWM Timer (PWMU) The lower four bits in PWMREG specify the position of pulses added to the 16 basic pulses. The additional pulse adds a high period (when PHnS = 0) at the resolution width before the rising edge of the basic pulse.
Page 242 Section 8 8-Bit PWM Timer (PWMU) Example of Setting 1 conversion period PWMREG setting Basic Additional example waveform pulses Duty cycle H'7F 127/256 112 pulses 15 pulses H'80 128/256 128 pulses 0 pulse H'81 129/256 128 pulses 1 pulse H'82 130/256 128 pulses 2 pulses...
Page 243: Usage Note
Section 8 8-Bit PWM Timer (PWMU) Usage Note 8.5.1 Setting Module Stop Mode The module stop control register can be used to enable or disable PWMU operation. The default setting disables PWMU operation. Clearing the module stop mode enables registers to be accessed.
Page 244 Section 8 8-Bit PWM Timer (PWMU) Rev. 1.00 Apr. 28, 2008 Page 218 of 994 REJ09B0452-0100...
Page 245: Section 9 14-Bit Pwm Timer (Pwmx)
Section 9 14-Bit PWM Timer (PWMX) Section 9 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Features •...
Page 246: Input/Output Pins
Section 9 14-Bit PWM Timer (PWMX) Input/Output Pins Table 9.1 lists the PWMX (D/A) module input and output pins. Table 9.1 Pin Configuration Pin Name Abbreviation I/O Function PWMX output pin 0 PWX0 Output PWMX output of channel A PWMX output pin 1 PWX1 Output PWMX output of channel B...
Page 247: Pwmx (D/A) Counter (Dacnt)
Section 9 14-Bit PWM Timer (PWMX) 9.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits.
Page 248: Pwmx (D/A) Data Registers A And B (Dadra And Dadrb)
Section 9 14-Bit PWM Timer (PWMX) 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP).
Page 249 Section 9 14-Bit PWM Timer (PWMX) • DADRB Initial Bit Name Value Description DA13 D/A Data 13 to 0 DA12 These bits set a digital value to be converted to an analog value. DA11 In each base cycle, the DACNT value is continually DA10 compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to...
Page 250: Pwmx (D/A) Control Register (Dacr)
Section 9 14-Bit PWM Timer (PWMX) 9.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Initial Bit Name Value Description  R/W` Reserved The initial value should not be changed. PWME PWMX Enable Starts or stops the PWM D/A counter (DACNT).
Page 251: Peripheral Clock Select Register (Pcsr)
Section 9 14-Bit PWM Timer (PWMX) 9.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Initial Bit Name Value Description  Reserved  The initial value should not be changed. PWCKXB PWMX clock select PWCKXA These bits select a clock cycle with the CKS bit of DACR of PWMX being 1.
Page 252: Bus Master Interface
Section 9 14-Bit PWM Timer (PWMX) Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP).
Page 253 Section 9 14-Bit PWM Timer (PWMX) Table 9.4 Reading/Writing to 16-bit Registers Read Write Register Word Byte Word Byte × DADRA, DADRB × × DACNT [Legend] Enabled access. Word-unit access includes accessing byte sequentially, first upper byte, and then lower byte.
Page 254 Section 9 14-Bit PWM Timer (PWMX) (a) Read upper byte Module data bus [H'AA] Bus interface Upper byte TEMP [H'57] DACNTH DACNTL [H'AA] [H'57] (b) Read lower byte Module data bus [H'57] Bus interface Lower byte TEMP [H'57] DACNTH DACNTL Figure 9.2 DACNT Access Operation (2) [DACNT →...
Page 255: Operation
Section 9 14-Bit PWM Timer (PWMX) Operation A PWM waveform like the one shown in figure 9.3 is output from the PWMX pin. DA13 to DA0 in DADR corresponds to the total width (T ) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1).
Page 256 Section 9 14-Bit PWM Timer (PWMX) Settings and Operation (Examples when φ = 20 MHz) Table 9.5 PCSR Fixed DADR Bits Reso- PWCKX0 lution Conver- PWCKX1 Bit Data Conversion Accuracy Base sion TL/TH (Bits) (µs) Cycle Cycle (OS = 0/OS = 1) Cycle* ...
Page 257 Section 9 14-Bit PWM Timer (PWMX) PCSR Fixed DADR Bits Reso- PWCKX0 lution Conver- PWCKX1 Bit Data Conversion Accuracy Base sion TL/TH (Bits) (µs) Cycle Cycle (OS = 0/OS = 1) Cycle* 12.8 819.2 209.7 Always low/high output 209.7 ms DA13 to 0 = H'0000 to H'00FF (µs) (ms)
Page 258 Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle f255 f256 L255 L256 = ··· = t = T× 64 f255 f256 + ··· + t L255 L256 (a) CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle = ···...
Page 259 Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle f255 f256 H255 H256 = ··· = t = T× 64 f255 f256 + ··· + t H255 H256 (a) CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle = ···...
Page 260 Section 9 14-Bit PWM Timer (PWMX) In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 9.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 ×...
Page 261 Section 9 14-Bit PWM Timer (PWMX) Table 9.6 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) Rev. 1.00 Apr. 28, 2008 Page 235 of 994 REJ09B0452-0100...
Page 262: Usage Notes
Section 9 14-Bit PWM Timer (PWMX) Usage Notes 9.6.1 Module Stop Mode Setting PWMX operation can be enabled or disabled by using the module stop control register. In the initial state, PWMX operation is disabled. Register access is enabled by clearing module stop mode.
Page 263: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively.
Page 264 Section 10 16-Bit Timer Pulse Unit (TPU) Clock input φ/1 Internal clock: φ/4 φ/16 φ/64 Internal data bus φ/256 φ/1024 A/D converter convertion External clock: TCLKA start signal TCLKB TCLKC TCLKD Input/output pins Interrupt request signals Channel 0: TGI0A Channel 0: TIOCA0 TGI0B TIOCB0...
Page 265 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/64 φ/64 φ/64 φ/256 φ/1024 TCLKA TCLKB TCLKA TCLKA TCLKC TCLKB TCLKB TCLKD TCLKC...
Page 266 Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 A/D converter trigger TGRA_0 compare TGRA_1 compare TGRA_2 compare match or input capture match or input capture match or input capture Interrupt sources 5 sources 4 sources 4 sources •...
Page 267: Input/Output Pins
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.2 Pin Configuration Channel Pin Name Function TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input...
Page 268: Register Descriptions
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers. Table 10.3 Register Configuration Initial Data Bus Channel Register Name Abbreviation R/W Value Address Width Channel 0 Timer control register_0 TCR_0 H'00 H'FE50 Timer mode register_0 TMDR_0 H'C0 H'FE51...
Page 269: Timer Control Register (Tcr)
Section 10 16-Bit Timer Pulse Unit (TPU) Initial Data Bus Channel Register Name Abbreviation R/W Value Address Width Channel 2 Timer general register A_2 TGRA_2 H'FFFF H'FE78 Timer general register B_2 TGRB_2 H'FFFF H'FE7A 16 Common Timer start register TSTR H'00 H'FEB0 8 Timer synchro register...
Page 270 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.4 CCLR2 to CCLR0 (channel 0) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing...
Page 271 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.6 TPSC2 to TPSC0 (channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 272 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.8 TPSC2 to TPSC0 (channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 273: Timer Mode Register (Tmdr)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped.
Page 274 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.9 MD3 to MD0 Bit 3 Bit2 Bit 1 Bit 0 Description MD3* MD2* Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 275: Timer I/O Control Register (Tior)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting.
Page 276 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.10 TIORH_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 277 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.11 TIORH_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 278 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.12 TIORL_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled Compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 279 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.13 TIORL_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 1 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 280 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.14 TIOR_1 (channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 281 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.15 TIOR_1 (channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 282 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.16 TIOR_2 (channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 283 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.17 TIOR_2 (channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 284: Timer Interrupt Enable Register (Tier)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Initial Bit Name value Description TTGE A/D Conversion Start Request Enable...
Page 285 Section 10 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 286: Timer Status Register (Tsr)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Initial Bit Name value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channel 1 and 2.
Page 287 Section 10 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFD R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Page 288 Section 10 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFB R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register •...
Page 289: Timer Counter (Tcnt)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units;...
Page 290: Timer Synchro Register (Tsyr)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to Initial Bit Name value...
Page 291: Interface To Bus Master
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 Interface to Bus Master 10.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units;...
Page 292 Section 10 16-Bit Timer Pulse Unit (TPU) Internal data bus Module master Bus interface data bus Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus Module master...
Page 293: Operation
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Operation 10.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of free- running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Page 294 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 295 Section 10 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software activation Figure 10.8 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 296 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B.
Page 297 Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. Example of input capture operation setting procedure Figure 10.12 shows an example of the input capture operation setting procedure.
Page 298 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 10.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 299: Synchronous Operation
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 300 Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 301: Buffer Operation
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 302 Section 10 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure Figure 10.18 shows an example of the buffer operation setting procedure. Buffer operation Designate TGR as an input capture register or output compare register by means of TIOR. Designate TGR for buffer operation with bits Select TGR function BFA and BFB in TMDR.
Page 303 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 304 Section 10 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 305: Pwm Modes
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty.
Page 306 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0 TGRA_1 TIOCA1 TIOCA1 TGRB_1 TIOCB1 TGRA_2 TIOCA2 TIOCA2...
Page 307 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation Figure 10.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value.
Page 308 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA TCNT value Output does not change when cycle register and duty register TGRB rewritten compare matches occur simultaneously...
Page 309: Phase Counting Mode
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 310 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.21 summarizes the TCNT up/down-count conditions.
Page 311 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count...
Page 312 Section 10 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count...
Page 313 Section 10 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.24 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 314: Interrupts
Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 Interrupts 10.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually.
Page 315: A/D Converter Activation
Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
Page 316: Operation Timing
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 Operation Timing 10.7.1 Input/Output Timing TCNT Count Timing Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT...
Page 317 Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 318 Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. φ...
Page 319 Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 10.36 and 10.37 show the timing in buffer operation. φ TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 10.36 Buffer Operation Timing (Compare Match) φ Input capture signal N + 1...
Page 320: Interrupt Signal Timing
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ...
Page 321 Section 10 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 322 Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 10.42 shows the timing for status flag clearing by the CPU. TSR write cycle φ...
Page 323: Usage Notes
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8 Usage Notes 10.8.1 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 324: Conflict Between Tcnt Write And Clear Operations
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.3 Conflict between TCNT Write and Clear Operations If the counter clear signal is generated in the T state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.44 shows the timing in this case. TCNT write cycle φ...
Page 325: Conflict Between Tgr Write And Compare Match
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.5 Conflict between TGR Write and Compare Match If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written.
Page 326: Conflict Between Tgr Read And Input Capture
Section 10 16-Bit Timer Pulse Unit (TPU) TGR write cycle φ Buffer register Address address Write signal Compare match signal Buffer register write data Buffer register Figure 10.47 Conflict between Buffer Register Write and Compare Match 10.8.7 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Page 327: Conflict Between Tgr Write And Input Capture
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.8 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.49 shows the timing in this case.
Page 328: 10.8.10 Conflict Between Overflow/Underflow And Counter Clearing
Section 10 16-Bit Timer Pulse Unit (TPU) Buffer register write cycle φ Buffer register Address address Write signal Input capture signal TCNT Buffer register Figure 10.50 Conflict between Buffer Register Write and Input Capture 10.8.10 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence.
Page 329: 10.8.11 Conflict Between Tcnt Write And Overflow/Underflow
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.11 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Page 330 Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Apr. 28, 2008 Page 304 of 994 REJ09B0452-0100...
Page 331: Section 11 16-Bit Cycle Measurement Timer (Tcm)
Section 11 16-Bit Cycle Measurement Timer (TCM) Section 11 16-Bit Cycle Measurement Timer (TCM) This LSI has four channels on-chip 16-bit cycle measurement timers (TCM). Each TCM has a 16- bit counter that provides the basis for measuring the periods of input waveforms. 11.1 Features •...
Page 332 Section 11 16-Bit Cycle Measurement Timer (TCM) Figure 11.1 is a block diagram of the TCM. External clock Internal clock φ/2, φ/8, φ/16, φ/32 TCMCKI φ/64, φ/128, φ/256 Clock selection Overflow TCMCNT Clear Control Compare matrch logic Comparator TCMMCI Cycle upper limit overflow Cycle lower limit underflow TCMMLCM TCMMINCM...
Page 333: Input/Output Pins
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.2 Input/Output Pins Table 11.1 lists the input and output pins for the TCMs. Table 11.1 Pin Configuration Channel Pin Name Function TCMCKI0 Input External counter clock input (TCMMCI0) Cycle measurement control input TCMCYI0 Input External event input...
Page 334 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Data Bus Channel Register Name Abbreviation R/W Value Address Width Channel 1 TCM timer counter_1 TCMCNT_1 H'0000 H'FBD0 16 TCM cycle upper limit register_1 TCMMLCM_1 R/W H'FFFF H'FBD2 16 TCM cycle lower limit register_1 TCMMINCM_1 R/W H'0000 H'FBDC 16 TCM input capture register_1...
Page 335: Tcm Timer Counter (Tcmcnt)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.1 TCM Timer Counter (TCMCNT) TCMCNT is a 16-bit readable/writable up-counter. The input clock is selected by the bits CKS2 to CKS0 in TCMCR. When CKS2 to CKS0 are set to B'111, the external clock is selected. In this case, the rising or falling edge is selected by CKSEG in TCMCR.
Page 336: Tcm Cycle Lower Limit Register (Tcmmincm)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.3 TCM Cycle Lower Limit Register (TCMMINCM) TCMMINCM is a 16-bit readable/writable register. TCMMINCM is available as a cycle lower limit register when the TCMMDS bit in TCMCR is set to 1 (operation is in cycle measurement mode).
Page 337: Tcm Status Register (Tcmcsr)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.6 TCM Status Register (TCMCSR) TCMCSR is an 8-bit readable/writable register that controls operation of the interrupt sources. Initial Bit Name Value Description R/(W)* Timer Overflow This flag indicates that the TCMCNT has overflowed. [Setting condition] Overflow of TCMCNT (change in value from H'FFFF to H'0000)
Page 338 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Bit Name Value Description ICPF R/(W)* Input Capture Generation Timer mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on generation of an input capture signal. This flag is set when the input capture signal is generated, i.e.
Page 339: Tcm Control Register (Tcmcr)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.7 TCM Control Register (TCMCR) TCMCR is an 8-bit readable/writable register. TCMCR selects input capture input edge, counter start, and counter clock, and controls operation mode. Initial Bit Name Value Description Counter Start In timer mode, setting this bit to 1 starts counting by TCMCNT;...
Page 340 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Bit Name Value Description IEDG Input Edge Select In timer mode, selects the falling or rising edge of the TCMCYI input for use in input capture, in combination with the value of the POCTL bit. In cycle measurement mode, selects the falling or rising edge of the TCMCYI input for use in measurement, in combination with the value of the POCTL bit.
Page 341: Tcm Interrupt Enable Register (Tcmier)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.8 TCM Interrupt Enable Register (TCMIER) TCMIER is an 8-bit readable/writable register that enables or disables interrupt requests. Initial Bit Name Value Description OVIE Counter Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the OVF flag in TCMCSR to 1.
Page 342 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Bit Name Value Description MINUDIE Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of the TUDI interrupt requests when the MINUDF flag in TCMCSR is set to 1. 0: Disable interrupt requests by MINUDF 1: Enable interrupt requests by MINUDF CMMS Cycle Measurement Mode Selection...
Page 343: Operation
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.4 Operation The TCM operates in timer mode or cycle measurement mode. TCM is in timer mode after a reset. 11.4.1 Timer Mode When the TCMMDS bit in TCMCR is cleared to 0, TCM operates in timer mode. Counter Operation TCMCNT operates as a free running counter in timer mode.
Page 344 Section 11 16-Bit Cycle Measurement Timer (TCM) Input Capture The value in TCMCNT is transferred to TCMICR by detecting input edge of TCMCYI pin in timer mode. At this time, the ICPF flag in TCMCSR is set. Detection of rising or falling edges is selectable with the setting of the IEDG bit in TCMCR.
Page 345: Cycle Measurement Mode
Section 11 16-Bit Cycle Measurement Timer (TCM) CMF Set Timing when a Compare Match occurs The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM match in timer mode. Therefore, a compare match signal is not generated until a further cycle of the TCMCNT input clock is generated after a match between the values in TCMCNT and TCMMLCM.
Page 346 Section 11 16-Bit Cycle Measurement Timer (TCM) Measuring a Cycle In cycle measurement mode, one cycle of the input waveform for TCM form one measurement cycle. Start by setting TCMMDS = 0 and then set CST = 0, which clears TCMCNT to H'0000. After that, set an upper or lower limit on the measurement cycle in the TCMMLCM/TCMMINCM register.
Page 347 Section 11 16-Bit Cycle Measurement Timer (TCM) When the CMMS bit in TCMIER is set to 1, cycle measurement is performed only while the TCMMCI signal is high (MCICTL in TCMCSR is 0). Figure 11.9 shows an example of timing in cycle measurement when the CMMS bit is set to 1.
Page 348 Section 11 16-Bit Cycle Measurement Timer (TCM) Cycle measurement stops if MAXOVF/MINUDF is set to 1 while the CPSPE bit in TCMCR is set to 1. Subsequently clearing MAXOVF/MINUDF to 0 restarts cycle measurement. In this case, the external event can be considered to have stopped if a timer overflow is generated before detection of the first edge.
Page 349 Section 11 16-Bit Cycle Measurement Timer (TCM) Example of Settings for Cycle Measurement Mode Figure 11.12 shows an example of the flow when cycle measurement mode is to be used. Start Initialization Set timer mode. Set TCMMDS to 0 Stop TCMCNT and initialize to H'0000. Set CST (TCMCR) to 0 Set an upper limit on the measurement period.
Page 350: Interrupt Sources
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.5 Interrupt Sources TCM has five interrupt sources: TICI, TCMI, TOVMI, TUDI, and TOVI. Each interrupt source is either enabled or disabled by the corresponding interrupt enable bit in TCMIER and independently transferred to the interrupt controller. Since a single vector address is allocated for each type of interrupt source from all channels, the flags must be used to discriminate between the sources.
Page 351: Usage Notes
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6 Usage Notes 11.6.1 Conflict between TCMCNT Write and Count-Up Operation When a conflict between TCMCNT write and count-up operation occurs in the second half of the TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority. Figure 11.13 shows the timing of this conflict.
Page 352: Conflict Between Tcmicr Read And Input Capture
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.3 Conflict between TCMICR Read and Input Capture When operation is in timer mode and the corresponding input capture signal is detected during reading of TCMICR, the input capture signal is delayed by one system clock (φ). Figure 11.15 shows the timing of this conflict.
Page 353: Conflict Between Edge Detection In Cycle Measurement Mode And Clearing Of Tcmmds Bit In Tcmcr
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and Clearing of TCMMDS Bit in TCMCR If the CST bit in TCMCR is set to 1 in cycle measurement mode, and the TCMMDS bit in TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of the selected edge will cause the timer to continue to operate in cycle measurement mode.
Page 354 Section 11 16-Bit Cycle Measurement Timer (TCM) Rev. 1.00 Apr. 28, 2008 Page 328 of 994 REJ09B0452-0100...
Page 355: Section 12 16-Bit Duty Period Measurement Timer (Tdp)
Section 12 16-Bit Duty Period Measurement Timer (TDP) Section 12 16-Bit Duty Period Measurement Timer (TDP) This LSI has a three-channel, 16-bit duty period measurement timer (TDP). The TDP uses a 16-bit counter as the basis for measuring input waveforms and the pulse width. 12.1 Features •...
Page 356 Section 12 16-Bit Duty Period Measurement Timer (TDP) Figure 12.1 shows a block diagram of the TDP. External clock Internal clock φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64 TDPCKI Clock selection Overflow TDPCNT Clear Compare match Comparator TDPMCI Cycle upper limit overflow Cycle lower limit underflow Pulse width upper limit overflow Pulse width lower limit underflow...
Page 357: Input/Output Pins
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the TDP. Table 12.1 Pin Configuration Channel Pin Name Function TDPCKI0 Input External counter clock input (TDPMCI0) Cycle measurement control input TDPCYI0 Input External event input TDPCKI1...
Page 358 Section 12 16-Bit Duty Period Measurement Timer (TDP) Data Initial Channel Register Name Abbreviation Value Address Width Channel 1 TDP timer counter_1 TDPCNT_1 H'0000 H'FB60 TDP pulse width upper limit register_1 TDPWDMX_1 H'FFFF H'FB62 TDP pulse width lower limit register_1 TDPWDMN_1 H'0000 H'FB64...
Page 359: Tdp Timer Counter (Tdpcnt)
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.1 TDP Timer Counter (TDPCNT) TDPCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to CKS0 in TDPCR1. When CKS2 to CKS0 are set to B'111, the external clock is selected. Rising or falling edge is selected by CKSEG in TDPCSR.
Page 360: Tdp Pulse Width Lower Limit Register (Tdpwdmn)
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.3 TDP Pulse Width Lower Limit Register (TDPWDMN) TDPWDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1 (cycle measurement mode), TDPWDMN is available as a pulse width lower limit register. In cycle measurement mode, TDPWDMN can be used to set the lower limit value of measurement pulse width.
Page 361: Tdp Input Capture Register (Tdpicr)
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.6 TDP Input Capture Register (TDPICR) TDPICR is a 16-bit read-only register. In timer mode, the TDPCNT value is transferred to TDPICR on the edge selected by the IEDG bit in TDPCR1, and the ICPF flag in TDPCSR is set to 1.
Page 362 Section 12 16-Bit Duty Period Measurement Timer (TDP) Initial Bit Name Value Description TWDMNUDF 0 R/(W)* Pulse Width Lower Limit Underflow This flag indicates that the waveform pulse width measured in cycle measurement mode is below the lower limit specified in TDPWDMN. [Setting condition] •...
Page 363 Section 12 16-Bit Duty Period Measurement Timer (TDP) Initial Bit Name Value Description R/(W)* Compare Match Flag (valid only in timer mode) [Setting condition] • When the TDPCNT value matches the TDPWDMX value in timer mode [Clearing condition] • Reading CMF when CMF = 1 and then writing 0 to Note: In cycle measurement mode, even though the TDPCNT value matches the TDPWDMX value, CMF is not set to 1.
Page 364: Tdp Control Register 1 (Tdpcr1)
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.9 TDP Control Register 1 (TDPCR1) TDPCR1 selects the input capture input edge, starts the TDPCNT counter, selects the counter clock, and controls the operating mode. Initial Bit Name Value Description Counter Start In timer mode, setting this bit to 1 starts counting by TDPCNT, and clearing it stops counting.
Page 365 Section 12 16-Bit Duty Period Measurement Timer (TDP) Initial Bit Name Value Description IEDG Input Edge Select In timer mode, in combination with the value of the POCTL bit, selects the falling or rising edge of the TDPCYI input for capturing input.
Page 366: Tdp Control Register 2 (Tdpcr2)
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.10 TDP Control Register 2 (TDPCR2) TDPCR2 selects cycle measurement mode and controls the TDPMCI input polarity. Initial Bit Name Value Description PMMS Cycle Measurement Mode Select Selects whether to use the TDPMCI signal in cycle measurement mode.
Page 367: Tdp Interrupt Enable Register (Tdpier)
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.11 TDP Interrupt Enable Register (TDPIER) TDPIER enables or disables interrupt requests and controls whether to enable or disable external event input. Initial Bit Name Value R/W Description OVIE Counter Overflow Interrupt Enable Enables or disables the issuing of OVF interrupt requests when the OVF flag in TDPCSR is set to 1.
Page 368 Section 12 16-Bit Duty Period Measurement Timer (TDP) TDPIPE Input Capture Input Enable Enables or disables TDPCYI pin input. To use input capture and cycle measurement mode, set this bit to 1. 0: Disabled 1: Enabled Note: Change this bit when CST = 0 and TDPMDS = 0. TPDMNIE Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of TPDMNUDF interrupt...
Page 369: Operation
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.4 Operation The TDP operates in timer mode or cycle measurement mode. After a reset, the TDP is in timer mode. 12.4.1 Timer Mode When the TDPMDS bit in TDPCR1 is cleared to 0, the TDP operates in timer mode. Counter Operation The TDP operates as a free-running counter in timer mode.
Page 370 Section 12 16-Bit Duty Period Measurement Timer (TDP) Input Capture The value in TDPCNT is transferred to TDPICR by detecting the input edge of the TDPCYI pin in timer mode. At the same time, the ICPF flag in TDPCSR is set. Detection of rising or falling edges is selectable by setting the IEDG bit in TDPCR1.
Page 371: Cycle Measurement Mode
Section 12 16-Bit Duty Period Measurement Timer (TDP) CMF Setting Timing when a Compare Match Occurs The CMF flag in TDPCSR is set in the last state in which the values in TDPCNT and TDPWDMX match (timing when TDPCNT updates the matched count value) in timer mode. Accordingly, a compare match signal is not generated until an additional cycle of the TDPCNT input clock is generated after a match between the values in TDPCNT and TDPWDMX.
Page 372 Section 12 16-Bit Duty Period Measurement Timer (TDP) Measuring a Cycle In cycle measurement mode, one cycle of the TDP input waveform forms one measurement cycle. Start by setting TDPMDS = 0 and CST = 0, which clears TDPCNT to H'0000. Next, set the upper limit and lower limit values of the measurement pulse width in TDPWDMX and TDPWDMN, and set the upper limit and lower limit values of the measurement cycle in the TDPPDMX and TDPPDMN.
Page 373 Section 12 16-Bit Duty Period Measurement Timer (TDP) Figure 12.8 shows an example of timing in cycle measurement. φ TDPCYI TDPCNT clear signal TDPCNT input clock TDPCNT H'0000 H'0001 N - 1 H'0000 H'0001 TDPICR TDPWDMX/TDPWDMN/ TDPPDMX/TDPPDMN TDPICRF Figure 12.8 Example of Timing in Cycle Measurement When the PMMS bit in TDPCR2 is set to 1, cycle measurement is performed only while the TDPMCI signal is high.
Page 374 Section 12 16-Bit Duty Period Measurement Timer (TDP) Determination of External Event (TDPCYI) Stoppage Stoppage for an external event (TDPCYI) can be determined from the timer overflow flag. There are two types of such stoppage. Stoppage for an external event can be considered to have occurred when the timer overflows within the period from the start of cycle measurement mode to the detection of the first edge (rising or falling, as selected by the POCTL bit in TDPCR1).
Page 375 Section 12 16-Bit Duty Period Measurement Timer (TDP) Setting Example of Setting Cycle Measurement Mode Figure 12.12 shows an example of a flowchart for using cycle measurement mode. Start Initial setting Set TDPMDS = 0 Set timer mode. Stop TDPCNT and initialize it to H'0000. Set CST = 0 Set pulse width upper limit value.
Page 376: Interrupt Sources
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.5 Interrupt Sources The TDP has seven interrupt sources; TICI, TCMI, TWDMXI, TWDMNI, TPDMXI, TPDNMI, and TOVI. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TDPIER and is independently transferred to the interrupt controller. Table 12.3 lists the interrupt sources in order of priority.
Page 377: Usage Notes
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6 Usage Notes 12.6.1 Conflict between TDPCNT Write and Count-Up Operation If a conflict between a TDPCNT write and counting up operation occurs in the second half of the TDPCNT write cycle, writing to TDPCNT takes precedence and TDPCNT is not incremented. Figure 12.13 shows the timing of this conflict.
Page 378: Conflict Between Input Capture And Tdpicr Read
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6.3 Conflict between Input Capture and TDPICR Read When the corresponding input capture signal is detected during reading of TDPICR in timer mode, the input capture signal is delayed by one cycle of the system clock (φ). Figure 12.15 shows the timing of this conflict.
Page 379: Conflict Between Edge Detection In Cycle Measurement Mode And Tdpmds Bit Clearing
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6.5 Conflict between Edge Detection in Cycle Measurement Mode and TDPMDS Bit Clearing When the TDPMDS bit in TDPCR1 is cleared in cycle measurement mode while the CST bit in TDPCR1 is 1 and the edge of TDPCYI is detected at the same time, the detected edge signal will cause the timer to continue to operate in cycle measurement mode.
Page 380 Section 12 16-Bit Duty Period Measurement Timer (TDP) Rev. 1.00 Apr. 28, 2008 Page 354 of 994 REJ09B0452-0100...
Page 381: Section 13 8-Bit Timer (Tmr)
Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 382 Section 13 8-Bit Timer (TMR) Figures 13.1 and 13.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X. External clock sources Internal clock sources TMR_0 TMI0 (TMCI0) φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024 TMI1 (TMCI1) TMR_1 φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048 Clock 1...
Page 383 Section 13 8-Bit Timer (TMR) Internal clock sources External clock sources TMR_X TMIY (TMCIY) φ, φ/2, φ/4, φ/2048, φ/4096, φ/8192 TMIX (TMCIX) TMR_Y φ/4, φ/256, φ/2048, φ/4096, φ/8192, φ/16384 Clock X Clock Y Clock selection TCORA_Y TCORA_X Compare-match AX Comparator A_Y Comparator A_X Compare-match AY Overflow X...
Page 384: Input/Output Pins
Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration Channel Pin Name Function TMR_0 TMO0 Output Output controlled by compare-match TMI0 Input External clock input/external reset input for the (TMCI0/TMRI0) counter TMR_1...
Page 385: Register Descriptions
Section 13 8-Bit Timer (TMR) 13.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). Table 13.2 Register Configuration Data Initial Channel Register Name Abbreviation R/W Value Address Width...
Page 386: Timer Counter (Tcnt)
Section 13 8-Bit Timer (TMR) Data Initial Channel Register Name Abbreviation R/W Value Address Width Channel X Timer counter_X TCNT_X H'00 H'FFF4 Time constant register A_X TCORA_X H'FF H'FFF6 Time constant register B_X TCORB_X H'FF H'FFF7 Timer control register_X TCR_X H'00 H'FFF0 Timer control/status register_X TCSR_X...
Page 387: Time Constant Register A (Tcora)
Section 13 8-Bit Timer (TMR) 13.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_X and TCORA_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1.
Page 388: Timer Control Register (Tcr)
Section 13 8-Bit Timer (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Initial Bit Name Value Description CMIEB Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Page 389 Section 13 8-Bit Timer (TMR) Table 13.3 Clock Input to TCNT and Count Condition (1) STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description TMR_0 — — Disables clock input — Increments at falling edge of internal clock φ/8 — Increments at falling edge of internal clock φ/2 —...
Page 390 Section 13 8-Bit Timer (TMR) STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Common — — Increments at rising edge of external clock — — Increments at falling edge of external clock — — Increments at both rising and falling edges of external clock Note: If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock...
Page 391 Section 13 8-Bit Timer (TMR) Clock Input to TCNT and Count Condition (2) TCRXY Channel CKS2 CKS1 CKS0 CKSX CKSY Description TMR_Y — Disables clock input Increments at φ/4 — Increments at φ/256 — Increments at φ/2048 — — Disables clock input —...
Page 392 Section 13 8-Bit Timer (TMR) TCRXY Channel CKS2 CKS1 CKS0 CKSX CKSY Description TMR_X — Disables clock input Increments at φ — Increments at φ/2 — Increments at φ/4 — — Disables clock input — Disables clock input Increments at φ/2048 —...
Page 393: Timer Control/Status Register (Tcsr)
Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. • TCSR_0 Initial Bit Name Value Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA...
Page 394 Section 13 8-Bit Timer (TMR) Initial Bit Name Value Description Output Select 1 and 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 395 Section 13 8-Bit Timer (TMR) Initial Bit Name Value Description Output Select 3 and 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Output Select 1 and 0...
Page 396 Section 13 8-Bit Timer (TMR) Initial Bit Name Value Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order.
Page 397 Section 13 8-Bit Timer (TMR) • TCSR_Y Initial Bit Name Value Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA R/(W)* Compare-Match Flag A [Setting condition]...
Page 398: Time Constant Register C (Tcorc)
Section 13 8-Bit Timer (TMR) Initial Bit Name Value Description Output Select 1 and 0 These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 399: Timer Connection Register I (Tconri)
Section 13 8-Bit Timer (TMR) 13.3.8 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Initial Bit Name Value Description 7 to 5 — All 0 Reserved The initial value should not be changed. ICST Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF).
Page 400: Timer Xy Control Register (Tcrxy)
Section 13 8-Bit Timer (TMR) Table 13.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TCR_X TCSR_X TICRR TICRF TCNT TCORC TCORA_X TCORB_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TCR_Y...
Page 401: Operation
Section 13 8-Bit Timer (TMR) 13.4 Operation 13.4.1 Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA.
Page 402: Operation Timing
Section 13 8-Bit Timer (TMR) 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges.
Page 403: Timing Of Cmfa And Cmfb Setting At Compare-Match
Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated.
Page 404: Timing Of Counter Clear At Compare-Match
Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match.
Page 405: Timing Of Overflow Flag (Ovf) Setting
Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00...
Page 406: Tmr_0 And Tmr_1 Cascaded Connection
Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available.
Page 407: Tmr_Y And Tmr_X Cascaded Connection
Section 13 8-Bit Timer (TMR) 13.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY.
Page 408: Input Capture Operation
Section 13 8-Bit Timer (TMR) 13.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF.
Page 409 Section 13 8-Bit Timer (TMR) Selection of Input Capture Signal Input TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 13.5. Table 13.5 Input Capture Signal Selection TCONRI Bit 4...
Page 410: Interrupt Sources
Section 13 8-Bit Timer (TMR) 13.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.6 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR.
Page 411: Usage Notes
Section 13 8-Bit Timer (TMR) 13.9 Usage Notes 13.9.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T state of a TCNT write cycle as shown in figure 13.13, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU φ...
Page 412: Conflict Between Tcor Write And Compare-Match
Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T state of a TCOR write cycle as shown in figure 13.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
Page 413: Switching Of Internal Clocks And Tcnt Operation
Section 13 8-Bit Timer (TMR) 13.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation.
Page 414 Section 13 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from high Clock before switchover to low level* Clock after switchover TCNT clock TCNT N + 1 N + 2 CKS bit rewrite Clock switching from high Clock before...
Page 415: Mode Setting With Cascaded Connection
Section 13 8-Bit Timer (TMR) 13.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating.
Page 416 Section 13 8-Bit Timer (TMR) Rev. 1.00 Apr. 28, 2008 Page 390 of 994 REJ09B0452-0100...
Page 417: Section 14 Watchdog Timer (Wdt)
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
Page 418 Section 14 Watchdog Timer (WDT) φ/2 φ/64 WOVI0 φ/128 Interrupt (Interrupt request signal) φ/512 control Clock Overflow Clock φ/2048 selection Internal NMI φ/8192 Reset (Interrupt request signal* φ/32768 control φ/131072 Internal clock Internal reset signal* TCNT_0 TCSR_0 interface Module bus WDT_0 φ/2 φSUB/2...
Page 419: Input/Output Pins
Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name Pin Name Function External sub-clock input pin EXCL Input Inputs the clock pulses to the WDT_1 prescaler counter 14.3 Register Descriptions The WDT has the following registers.
Page 420: Timer Counter (Tcnt)
Section 14 Watchdog Timer (WDT) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. •...
Page 421 Section 14 Watchdog Timer (WDT) Initial Bit Name Value Description RST/NMI Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested CKS2 Clock Select 2 to 0 CKS1...
Page 422 Section 14 Watchdog Timer (WDT) • TCSR_1 Initial Bit Name Value Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Page 423 Section 14 Watchdog Timer (WDT) Initial Bit Name Value Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow cycle for φ = 20 MHz and φSUB = 32.768 kHz CKS0 is enclosed in parentheses.
Page 424: Operation
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated.
Page 425: Interval Timer Mode
Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals.
Page 426: Interrupt Sources
Section 14 Watchdog Timer (WDT) 14.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine.
Page 427: Conflict Between Timer Counter (Tcnt) Write And Increment
Section 14 Watchdog Timer (WDT) <TCNT write> Address : H'FFA8 H'5A Write data <TCSR write> Address : H'FFA8 H'A5 Write data Figure 14.5 Writing to TCNT and TCSR (WDT_0) Reading from TCNT and TCSR (Example of WDT_0) These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT.
Page 428: Changing Values Of Cks2 To Cks0 Bits
Section 14 Watchdog Timer (WDT) 14.6.3 Changing Values of CKS2 to CKS0 Bits If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits.
Page 429: Section 15 Serial Communication Interface (Sci)
Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 430 Section 15 Serial Communication Interface (SCI) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors Smart Card Interface: • An error signal can be automatically transmitted on detection of a parity error during reception. • Data can be automatically re-transmitted on detection of an error signal during transmission. •...
Page 431: Input/Output Pins
Section 15 Serial Communication Interface (SCI) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration Channel Pin Name* Input/Output Function SCK1 Input/Output Channel 1 clock input/output RxD1 Input Channel 1 receive data input TxD1 Output Channel 1 transmit data output...
Page 432: Register Descriptions
Section 15 Serial Communication Interface (SCI) 15.3 Register Descriptions The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes ...
Page 433: Receive Shift Register (Rsr)
Section 15 Serial Communication Interface (SCI) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 434: Serial Mode Register (Smr)
Section 15 Serial Communication Interface (SCI) 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. The CPU can always read SMR.
Page 435 Section 15 Serial Communication Interface (SCI) Bit Name Initial Value Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 Clock Select 1 and 0 CKS0...
Page 436 Section 15 Serial Communication Interface (SCI) Bit Name Initial Value Description Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 15.7.2, Data Format (Except in Block Transfer Mode).
Page 437: Serial Control Register (Scr)
Section 15 Serial Communication Interface (SCI) 15.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 15.8, Interrupt Sources.
Page 438 Section 15 Serial Communication Interface (SCI) Bit Name Initial Value Description CKE1 Clock Enable 1 and 0 CKE0 These bits select the clock source and SCK pin function. • Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency...
Page 439 Section 15 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Page 440: Serial Status Register (Ssr)
Section 15 Serial Communication Interface (SCI) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Page 441 Section 15 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
Page 442 Section 15 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Name Initial Value Description TDRE R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 •...
Page 443 Section 15 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 TEND Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR.
Page 444: Smart Card Mode Register (Scmr)
Section 15 Serial Communication Interface (SCI) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Name Initial Value Description  7 to 4 All 1 Reserved These bits are always read as 1 and cannot be modified.
Page 445: Bit Rate Register (Brr)
Section 15 Serial Communication Interface (SCI) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.3 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode.
Page 446 Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 9.8304 Bit Rate Error Error Error Error (bit/s) 0.03 –0.26 –0.25 0.03 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16...
Page 447 Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 17.2032 19.6608 Bit Rate Error Error Error Error (bit/s) 0.48 –0.12 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00...
Page 448 Section 15 Serial Communication Interface (SCI) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) External Input Maximum Bit External Input Maximum Bit φ (MHz) φ (MHz) Clock (MHz) Rate (bit/s) Clock (MHz) Rate (bit/s) 2.0000 125000 14.7456 3.6864 230400 9.8304...
Page 449 Section 15 Serial Communication Interface (SCI) Table 15.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) External Input Maximum Bit External Input Maximum Bit φ (MHz) φ (MHz) Clock (MHz) Rate (bit/s) Clock (MHz) Rate (bit/s) 1.3333 1333333.3 2.6667 2666666.7 1.6667...
Page 450: Operation In Asynchronous Mode
Section 15 Serial Communication Interface (SCI) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level).
Page 451: Data Transfer Format
Section 15 Serial Communication Interface (SCI) 15.4.1 Data Transfer Format Table 15.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 15.5, Multiprocessor Communication Function.
Page 452: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Section 15 Serial Communication Interface (SCI) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 453: Clock
Section 15 Serial Communication Interface (SCI) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
Page 454: Sci Initialization (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 455: Serial Data Transmission (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.4.5 Serial Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 456 Section 15 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 457: Serial Data Reception (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 458 Section 15 Serial Communication Interface (SCI) Table 15.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Page 459 Section 15 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 460 Section 15 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 461: Multiprocessor Communication Function
Section 15 Serial Communication Interface (SCI) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 462 Section 15 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle =...
Page 463: Multiprocessor Serial Data Transmission
Section 15 Serial Communication Interface (SCI) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.
Page 464: Multiprocessor Serial Data Reception
Section 15 Serial Communication Interface (SCI) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 465 Section 15 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] ID reception cycle: Set MPIE bit in SCR to 1 Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR [3] SCI status check, ID reception and comparison:...
Page 466 Section 15 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 467: Operation In Clocked Synchronous Mode
Section 15 Serial Communication Interface (SCI) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 468: Sci Initialization (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 469: Serial Data Transmission (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 470 Section 15 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request Data written to TDR and TXI interrupt request TEI interrupt request generated TDRE flag cleared to 0 in generated...
Page 471: Serial Data Reception (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 472 Section 15 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 473: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Section 15 Serial Communication Interface (SCI) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 474 Section 15 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin Start transmission/reception is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag...
Page 475: Smart Card Interface Description
Section 15 Serial Communication Interface (SCI) 15.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 15.7.1 Sample Connection Figure 15.21 shows a sample connection between the smart card and this LSI.
Page 476: Data Format (Except In Block Transfer Mode)
Section 15 Serial Communication Interface (SCI) 15.7.2 Data Format (Except in Block Transfer Mode) Figure 15.22 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame.
Page 477: Block Transfer Mode
Section 15 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 15.23. Therefore, data in the start character in the figure is H'3B.
Page 478: Receive Data Sampling Timing And Reception Margin
Section 15 Serial Communication Interface (SCI) 15.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 479: Initialization
Section 15 Serial Communication Interface (SCI) 15.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2.
Page 480 Section 15 Serial Communication Interface (SCI) 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1.
Page 481 Section 15 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0 ? Error processing TEND = 1 ? Write data to TDR and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0 ? Error processing TEND = 1 ? Clear TE bit in SCR to 0 Figure 15.28 Sample Transmission Flowchart...
Page 482: Serial Data Reception (Except In Block Transfer Mode)
Section 15 Serial Communication Interface (SCI) 15.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 15.29 shows the data re-transfer operation during reception. 1.
Page 483 Section 15 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? Error processing RDRF = 1 ? Read data from RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit in SCR to 0 Figure 15.30 Sample Reception Flowchart Rev.
Page 484: Clock Output Control
Section 15 Serial Communication Interface (SCI) 15.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0.
Page 485 Section 15 Serial Communication Interface (SCI) At Transition from Smart Card Interface Mode to Software Standby Mode 1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. 2.
Page 486: Interrupt Sources
Section 15 Serial Communication Interface (SCI) 15.8 Interrupt Sources 15.8.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR.
Page 487: Interrupts In Smart Card Interface Mode
Section 15 Serial Communication Interface (SCI) 15.8.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 15.14 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag...
Page 488: Usage Notes
Section 15 Serial Communication Interface (SCI) 15.9 Usage Notes 15.9.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 26, Power-Down Modes.
Page 489: Sci Operations During Mode Transitions
Section 15 Serial Communication Interface (SCI) 15.9.6 SCI Operations during Mode Transitions Transmission Before making the transition to module stop or software standby, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the TE is set to 1 again.
Page 490 Section 15 Serial Communication Interface (SCI) Transition to Software standby software standby Transmission start Transmission end mode cancelled mode TE bit Port input/output output pin Port High output Start Stop Port input/output High output output pin input/output SCI TxD output Port Port TxD output...
Page 491 Section 15 Serial Communication Interface (SCI) Reception Before making the transition to module stop, software standby or watch mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid.
Page 492: Notes On Switching From Sck Pins To Port Pins
Section 15 Serial Communication Interface (SCI) 15.9.7 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.40. Low pulse of half a cycle SCK/Port 1.
Page 493: Note On Writing To Registers In Transmission, Reception, And Simultaneous Transmission And Reception
Section 15 Serial Communication Interface (SCI) 15.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception After 1 is set to the TE and RE bits in SCR to start transmission, reception, and simultaneous transmission and reception, do not write to SMR, SCR, BRR, and SDCR. Also, do not overwrite the same value as the register value.
Page 494 Section 15 Serial Communication Interface (SCI) Rev. 1.00 Apr. 28, 2008 Page 468 of 994 REJ09B0452-0100...
Page 495: Section 16 Cir Interface
Section 16 CIR Interface Section 16 CIR Interface This LSI incorporates a custom infra-red interface (CIR). The CIR has various functions for receiving the IR signal in NEC format. 16.1 Features • Supports reception of the IR signal in NEC format •...
Page 496 Section 16 CIR Interface Module data bus HHMAX HHMIN CCR1 CIRRDR φ HLMAX HLMIN 0 to 17 CCR2 (18-byte φ/2 DT0MAX DT0MIN CSTR FIFO) Baud rate generator φ/4 DT1MAX DT1MIN φ CEIR RMAX RMIN CIRI 4-stage filter Reception control Sampling clock RENDI OVEI REPI...
Page 497: Input Pins
Section 16 CIR Interface 16.2 Input Pins Table 16.1 shows the input pin of the CIR. Table 16.1 Pin Configuration Pin Name Symbol Function CIR input pin CIRI Input CIR receive data input pin 16.3 Register Description Table 16.2 shows the CIR register configuration. Table 16.2 List of Register Addresses Register Name Abbreviation...
Page 498: Receive Control Register 1 (Ccr1)
Section 16 CIR Interface Register Name Abbreviation Initial Value Address Repeat header minimum low-level period RMIN H'00 H'FA50 register Repeat header maximum low-level period RMAX H'00 H'FA51 register Notes: 1. Before accessing these registers, clear the MSTPA3 bit (bit 3) in MSTPCRA to 0. 2.
Page 499: Receive Control Register 2 (Ccr2)
Section 16 CIR Interface Initial Bit Name Value Description REPRCVE Receive Enable after Repeat Detection Enables/disables the CIR reception after a repeat detection. 0: The CIR reception is disabled by a repeat detection. 1: The CIR reception is enabled by a repeat detection ...
Page 500: Receive Status Register (Cstr)
Section 16 CIR Interface 16.3.3 Receive Status Register (CSTR) CSTR indicates the data reception state of the CIR. Initial Bit Name Value Description CIRBUSY CIR Busy Flag Indicates the data receive state of the CIR. [Setting condition] When the CIR starts data reception. [Clearing condition] When the CIR has finished data reception.
Page 501 Section 16 CIR Interface Initial Bit Name Value Description REND R/W* Reception End Flag [Setting condition] When the CIR has finished data reception. (When a stop is detected.) [Clearing condition] When writing 0 after reading REND = 1. R/W* Abort Flag An internal reset is generated when an abort (transfer format) is detected.
Page 502: Interrupt Enable Register (Ceir)
Section 16 CIR Interface 16.3.4 Interrupt Enable Register (CEIR) CEIR consists of the bits that enable/disable various interrupts. Initial Bit Name Value Description  7, 6 All 0 Reserved The initial value should not be changed. REPIE Repeat Detection Interrupt Enable 0: REPI interrupt request is disabled.
Page 503: Bit Rate Register (Brr)
Section 16 CIR Interface 16.3.5 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the sampling clock signal used for CIR reception. The bit rate for the CIR reception is determined by a combination of the setting value in BRR and the CLK1 and CLK0 bits in CCR1.
Page 504: Receive Data Register 0 To 17 (Cirrdr0 To Cirrdr17)
Section 16 CIR Interface 16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17) CIRRDR0 to CIRRDR17 are an 18-byte register that stores receive data, totaling to 18 bytes. CIRRDR0 to CIRRDR17 share one byte of the register address. A receive data in CIRRDR should be read after the CIR has finished data reception (CIRBUSY = 0).
Page 505 Section 16 CIR Interface • HHMAX Initial Bit Name Value Description FLT1 Number of Stages of Noise Canceler Circuit Select FLT0 00: The noise canceler circuit consists of one stage 01: The noise canceler circuit consists of two stages 10: The noise canceler circuit consists of three stages 11: The noise canceler circuit consists of four stages FLTE...
Page 506: Header Minimum/Maximum Low-Level Period Register (Hlmin/Hlmax)
Section 16 CIR Interface 16.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX) HLMIN and HLMAX specify the minimum and maximum low-level period for a header. • HLMIN Initial Bit Name Value Description 7 to 0 HLMIN7 to H'00 Specifies the minimum low-level period for a header. HLMIN0 •...
Page 507: Data Level 0 Minimum/Maximum Period Register (Dt0Min/Dt0Max)
Section 16 CIR Interface 16.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) DT0MIN and DT0MAX specify the minimum and maximum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat. • DT0MIN Initial Bit Name Value Description 7 to 0...
Page 508: Operation
Section 16 CIR Interface 16.4 Operation The communication protocol of the NEC format is shown in figure 16.2. In the NEC format, data consists of a header part, an address part, a command part, and a stop part. The TFM bits in CCR2 can select which data bytes to be stored in CIRRDR: four bytes of the address, address, command, and command, or two bytes of the address and command.
Page 509 Section 16 CIR Interface Stop When a low-level period of 9 ms or more is detected after the reception of a command, the CIR stops data reception. This is not defined in the NEC format. Command Stop CIRI A = 9.0 ms C = 0.56 ms D = 1.78 ms [Legend]...
Page 510: Determination Of Signal Type By Low/High-Level Period
Section 16 CIR Interface 16.4.1 Determination of Signal Type by Low/High-Level Period The signal type is determined by low/high-level period that is specified in the HHMIN, HHMAX, HLMIN, HLMAX, DT1MIN, DT1MAX, DT0MIN, DT0MAX, RMIN, and RMAX registers. Calculating formula for specified time, setting examples of each maximum/minimum value register during the specified time, and use for each register are described as follows.
Page 511 Section 16 CIR Interface Table 16.4 An Example of Signal Type Determination Register Setting Prescribed Register Setting Setting Time Description Name Symbol Value Time (Error: 30%) Notes Minimum high-level period HHMIN H'079 6.34 ms 6.3 ms HHMIN9 to for a header or repeat HHMIN0 header and minimum low- level period for a stop...
Page 512: Operation Of Fifo Register
Section 16 CIR Interface 16.4.2 Operation of FIFO Register A FIFO structure provides first-in first-out operation. Operation of the FIFO when it receives data three times (byte 0, byte 1, and byte 2 in order) and is then read three times is as shown below. Operation for first reception Operation for data reception of data...
Page 513: Operation In Watch Mode
Section 16 CIR Interface In case of reading more bytes than the number that has been received, (number of received bytes + 1) of data are always read out from the FIFO. Reception of more than 18 bytes by the FIFO structure for this CIR module leads to an overrun. When an overrun occurs, only values up to the 18th byte to have been received are read out in response to the reading of more than 18 bytes.
Page 514: Noise Canceler Circuit
Section 16 CIR Interface 16.5 Noise Canceler Circuit The CIR incorporates a 4-stage noise canceler. The FLTE, FLT, and FLTCK1 and FLTCK0 bits in HHMAX enable/disable the noise canceler circuit, select the number of stages of the noise canceler circuit, and select the division ratio for generating the noise canceler circuit clock, respectively.
Page 515 Section 16 CIR Interface Table 16.5 shows sample settings for the noise canceler circuit. Table 16.5 Sample Settings for Noise Canceler Circuit CLK1 and FLTCK1 and Number of Stages Width of CLK0 FLTCK0 Sampling of Noise Canceler Noise φ Setting Setting Setting Clock...
Page 516: Reset Conditions
Section 16 CIR Interface 16.6 Reset Conditions The range of initialization caused by a system reset, a software reset controlled by the SRES bit in CCR1, or an abort is shown in table 16.6. Table 16.6 Range of Initialization of CIR HHMIN, HHMAX, HLMIN, HLMAX, DT0MIN, DT0MAX,...
Page 517: Usage Note
Section 16 CIR Interface 16.8 Usage Note CIR Register Setting Before starting the CIR reception, set the CIR by following the flow shown in figure 16.7. Start of setting Clear MSTPA3 bit in MSTPCRA to 0. Set CPHS bit in CCR1. Set each register.
Page 518 Section 16 CIR Interface Overrun Operation with the NEC format (2 Bytes are Used) When the reception signal format select bits (bits TFM1 and TFM0 in CCR2) are set to the NEC format (2 bytes are used), the OVRF bit in CSTR is set to indicate the overrun on the reception of the 18th byte by the receive data register.
Page 519: Section 17 Serial Communication Interface With Fifo (Scif)
Section 17 Serial Communication Interface with FIFO (SCIF) Section 17 Serial Communication Interface with FIFO (SCIF) This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that supports asynchronous serial communication. The SCIF enables asynchronous serial communication with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART).
Page 520 Section 17 Serial Communication Interface with FIFO (SCIF) Figure 17.1 shows a block diagram of the SCIF. FIER PB2/RI FIIR PB3/DCD FFCR Modem PB4/DSR FLCR controller PB5/DTR FMCR PB6/CTS FLSR PB7/RTS FMSR FSCR FTHR interface Transmit FIFO (16 bytes) P50/FTxD FTSR Transmission Register...
Page 521: Input/Output Pins
Section 17 Serial Communication Interface with FIFO (SCIF) 17.2 Input/Output Pins Table 17.1 lists the SCIF input/output pins. Table 17.1 Pin Configuration Pin Name Port Input/Output Function FTxD Output Transmit data output FRxD Input Receive data input Input Ring indicator input Input Data carrier detect input Input...
Page 522: Register Descriptions
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3 Register Descriptions The SCIF has the following registers. The register configuration of the SCIF is shown below. Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details, see table 17.3.
Page 523: Receive Shift Register (Frsr)
Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.3 Register Access SCIFE Bit in HICR5 Bit 3 in MSTPCRB SCIFCR H8S CPU Access disabled H8S CPU Access disabled access* access* Other than SCIFCR H8S CPU Access disabled LPC access* LPC access* access* Notes: 1.
Page 524: Transmitter Shift Register (Ftsr)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.3 Transmitter Shift Register (FTSR) FTSR is a register that converts parallel data from the FTxD pin to serial data and then transmits the serial data. When one frame transmission of serial data is completed, the next data is transferred from FTHR.
Page 525: Interrupt Enable Register (Fier)
Section 17 Serial Communication Interface with FIFO (SCIF) • FDLL Bit Name Initial Value Description 7 to 0 Bit 7 to All 0 Lower 8 bits of divisor latch bit 0 Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value) 17.3.6 Interrupt Enable Register (FIER) FIER is a register that enables or disables interrupts.
Page 526: Interrupt Identification Register (Fiir)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.7 Interrupt Identification Register (FIIR) FIIR consists of bits that identify interrupt sources. For details, see table 17.4. Bit Name Initial Value Description FIFOE1 FIFO Enable 1, 0 FIFOE0 These bits indicate the transmit/receive FIFO setting. 00: Transmit/receive FIFOs disabled 11: Transmit/receive FIFOs enabled ...
Page 527 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.4 Interrupt Control Function FIIR Setting/Clearing of Interrupt INTID Clearing of INTPEND Priority Type of Interrupt Interrupt Source Interrupt  No interrupt None 1 (high) Receive line status Overrun error, FLSR read parity error, framing error, break interrupt...
Page 528: Fifo Control Register (Ffcr)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.8 FIFO Control Register (FFCR) FFCR is a write-only register that controls transmit/receive FIFOs. Bit Name Initial Value R/W Description RCVRTRIG1 Receive FIFO Interrupt Trigger Level 1, 0 RCVRTRIG0 These bits set the trigger level of the receive FIFO interrupt.
Page 529: Line Control Register (Flcr)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.9 Line Control Register (FLCR) FLCR sets formats of the transmit/receive data. Bit Name Initial Value Description DLAB Divisor Latch Address FDLL and FDLH are placed at the same addresses as the FRBR/FTHR and FIER addresses. This bit selects which register is to be accessed.
Page 530: Modem Control Register (Fmcr)
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value Description STOP Stop Bit Specifies the stop bit length for data transmission. For data reception, only the first stop bit is checked regardless of the setting. 0: 1 stop bit 1: 1.5 stop bits (data length: 5 bits) or 2 stop bits (data length: 6 to 8 bits) CLS1...
Page 531 Section 17 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value Description OUT2 OUT2 • Normal operation Enables or disables the SCIF interrupt. 0: Interrupt disabled 1: Interrupt enabled • Loopback test Internally connected to the DCD input pin. OUT1 OUT1 •...
Page 532: Line Status Register (Flsr)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.11 Line Status Register (FLSR) FLSR is a read-only register that indicates the status information of data transmission. Bit Name Initial Value R/W Description RXFIFOERR 0 Receive FIFO Error Indicates that at least one data error (parity error, framing error, or break interrupt) has occurred when the FIFO is enabled.
Page 533 Section 17 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description THRE FTHR Empty Indicates that FTHR is ready to accept new data for transmission. • When the FIFO is enabled 0: Transmit data of one or more bytes remains in the transmit FIFO.
Page 534 Section 17 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description Framing Error Indicates that the stop bit of the receive data is invalid. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer.
Page 535 Section 17 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description Overrun Error Indicates occurrence of an overrun error. • When the FIFO is disabled When reception of the next data has been completed without the receive data in FRBR having been read, an overrun error occurs and the previous data is lost.
Page 536: Modem Status Register (Fmsr)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.12 Modem Status Register (FMSR) FMSR is a read-only register that indicates the status of or a change in the modem control pins. Bit Name Initial Value R/W Description Undefined Data Carrier Detect Indicates the inverted state of the DCD input pin.
Page 537: Scratch Pad Register (Fscr)
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description DDSR Delta Data Set Ready Indicator Indicates a change in the DSR input signal after the DDSR bit is read. 0: No change in the DSR input signal after FMSR read [Clearing condition] FMSR read...
Page 538: Scif Control Register (Scifcr)
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.14 SCIF Control Register (SCIFCR) SCIFCR controls SCIF operations, and is accessible only from the CPU. Bit Name Initial Value R/W Description SCIFOE1 These bits enable or disable PORT output of the SCIF.
Page 539 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.5 SCIF Output Setting Bit 3 in HICR5 0 Bit 7 in SCIFCR Bit 6 in SCIFCR PB7 and PB5 PORT PORT SCIF PORT SCIF PORT SCIF PORT pins P50 pin PORT PORT SCIF...
Page 540: Operation
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4 Operation 17.4.1 Baud Rate The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH, FDLL, and the CKSEL bit in SCIFCR. Table 17.6 shows an example of baud rate settings. Table 17.6 Example of Baud Rate Settings LCLK System Clock...
Page 541: Operation In Asynchronous Communication
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.2 Operation in Asynchronous Communication Figure 17.2 illustrates the typical format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least significant bit), a parity bit, and a stop bit (high level).
Page 542: Initialization Of The Scif
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.3 Initialization of the SCIF Initialization of the SCIF Use an example of the flowchart in figure 17.3 to initialize the SCIF before transmitting or receiving data. Start initialization Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR.
Page 543 Section 17 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission Figure 17.4 shows an example of the data transmission flowchart. Initialization [1] Confirm that the THRE flag in FLSR is 1, and write transmit data to FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data.
Page 544 Section 17 Serial Communication Interface with FIFO (SCIF) Serial Data Reception Figure 17.5 shows an example of the data reception flowchart. Confirm that the DR flag in FLSR is 1 to ensure that Initialization receive data is in the buffer. When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1, a receive data ready interrupt occurs.
Page 545: Data Transmission/Reception With Flow Control
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.4 Data Transmission/Reception with Flow Control The following shows examples of data transmission/reception for flow control using CTS and RTS. Initialization Figure 17.6 shows an example of the initialization flowchart. Start initialization [1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR.
Page 546 Section 17 Serial Communication Interface with FIFO (SCIF) Data Transmission/Reception Standby Figure 17.7 shows an example of the data transmission/reception standby flowchart. [1] When a receive data ready interrupt Initialization occurs, go to the reception flow. [2] When transmit data exists, go to the transmission flow.
Page 547 Section 17 Serial Communication Interface with FIFO (SCIF) Data Transmission Figure 17.8 shows an example of the data transmission flowchart. [1] Confirm that the CTS flag in FMSR is 1. Transmission/reception standby [2] Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is empty.
Page 548 Section 17 Serial Communication Interface with FIFO (SCIF) Suspension of Data Transmission Figure 17.9 shows an example of the data transmission suspension flowchart. [1] Read the DCTS flag in FMSR in the modem Modem status change interrupt status change interrupt processing routine. If the DCTS flag is set to 1, the transmission suspension processing starts.
Page 549 Section 17 Serial Communication Interface with FIFO (SCIF) Data Reception Figure 17.10 shows an example of the data reception flowchart. [1] When data is received, a receive data ready Receive data ready interrupt interrupt occurs. Go to the data reception flow by using this interrupt trigger.
Page 550 Section 17 Serial Communication Interface with FIFO (SCIF) Suspension of Data Reception Figure 17.11 shows an example of the data reception suspension flowchart. [1] When data is received at a trigger level higher than Receive FIFO trigger level interrupt the receive FIFO trigger level specified in the initialization flow, a receive FIFO trigger level interrupt occurs.
Page 551: Data Transmission/Reception Through The Lpc Interface
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.5 Data Transmission/Reception Through the LPC Interface As shown in table 17.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception shown in figures 17.3 to 17.5 to be made from the LPC interface.
Page 552 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.8 shows the range of initialization of the registers related to data transmission/reception through the LPC interface, making a classification by each mode. Table 17.8 Register States System Register Reset SCIFRST REGRST Reset Shutdown Abort...
Page 553 Section 17 Serial Communication Interface with FIFO (SCIF) System Register Reset SCIFRST REGRST Reset Shutdown Abort FMCR LOOP BACK, Initialized Retained Initialized Initialized Retained Retained OUT2, OUT1, RTS, DTR FLSR RXFEFOERR, Initialized Retained Initialized Initialized Retained Retained TEMT, THRE, BI, FE, PE, OE, FMSR DDCD, TERI, Initialized Retained Initialized Initialized Retained...
Page 554: Interrupt Sources
Section 17 Serial Communication Interface with FIFO (SCIF) 17.5 Interrupt Sources Table 17.9 lists the interrupt sources. A common interrupt vector is assigned to each interrupt source. When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU. The SERIRQ signal of the LPC interface transmits an interrupt request to the host.
Page 555: Section 18 I C Bus Interface (Iic)
Section 18 I C Bus Interface (IIC) Section 18 I C Bus Interface (IIC) This LSI has a three-channel I C bus interface. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 556 Section 18 I C Bus Interface (IIC) • Selection of 16 internal clocks (in master mode) • Direct bus drive (SCL/SDA pin)  Ten pins—P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG2/SDA2, PG3/SCL2, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB —(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected.
Page 557 Section 18 I C Bus Interface (IIC) ICXR φ ICCR Clock control ExSCLA Noise ICMR ExSCLB canceler Bus state decision ICSR circuit Arbitration decision circuit ICDRT Output data control ICDRS circuit ExSDAA ExSDAB ICDRR Noise canceler Address comparator [Legend] ICCR: C bus control register ICMR: C bus mode register...
Page 558 Section 18 I C Bus Interface (IIC) (Master) This LSI (Slave 1) (Slave 2) Figure 18.2 I C Bus Interface Connections (Example: This LSI as Master) Rev. 1.00 Apr. 28, 2008 Page 532 of 994 REJ09B0452-0100...
Page 559: Input/Output Pins
Section 18 I C Bus Interface (IIC) 18.2 Input/Output Pins Table 18.1 summarizes the input/output pins used by the I C bus interface. One of three pins can be specified as SCL and SDA input/output pin for IIC_0 and IIC_1. Two or more input/output pins should not be specified for one channel.
Page 560: Register Descriptions
Section 18 I C Bus Interface (IIC) 18.3 Register Descriptions The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR.
Page 561 Section 18 I C Bus Interface (IIC) Initial Data Bus Channel Register Name Abbreviation R/W Value Address Width Channel 2 C bus extended control register_2 ICXR_2 R/W H'00 H'FE8C C bus control register_2 ICCR_2 R/W H'01 H'FE88 C bus status register_2 ICSR_2 R/W H'00 H'FE89...
Page 562: C Bus Data Register (Icdr)
Section 18 I C Bus Interface (IIC) 18.3.1 C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT).
Page 563: Slave Address Register (Sar)
Section 18 I C Bus Interface (IIC) 18.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 564: Second Slave Address Register (Sarx)
Section 18 I C Bus Interface (IIC) 18.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 565 Section 18 I C Bus Interface (IIC) Table 18.3 Communication Format SARX Operating Mode C bus format • SAR and SARX slave addresses recognized • General call address recognized C bus format • SAR slave address recognized • SARX slave address ignored •...
Page 566: C Bus Mode Register (Icmr)
Section 18 I C Bus Interface (IIC) 18.3.4 C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Initial Bit Name Value Description MSB-First/LSB-First Select 0: MSB-first...
Page 567 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low.
Page 568 Section 18 I C Bus Interface (IIC) Table 18.4 I C Transfer Rate STCR ICMR Bits 5, 6, and 7 Bit 5 Bit 4 Bit 3 Transfer Rate φ = 8 MHz φ = 10 MHz φ = 16 MHz φ...
Page 569: C Bus Control Register (Iccr)
Section 18 I C Bus Interface (IIC) 18.3.5 C Bus Control Register (ICCR) ICCR controls the I C bus interface and performs interrupt flag confirmation. Initial Bit Name Value Description C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized.
Page 570 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2.
Page 571 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description BBSY R/W* Bus Busy Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode: •...
Page 572 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description IRIC R/(W)* I C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
Page 573 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description IRIC R/(W)* Note: When the slave address does not match and the general call address is not detected (with all flags of AAS, AASX, and ADZ cleared to 0), transmission and reception do not proceed.
Page 574 Section 18 I C Bus Interface (IIC) When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer.
Page 575 Section 18 I C Bus Interface (IIC) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State 0↓ 0↓ — 1↑ — — — Arbitration lost — 0↓ — — — 0↓ Stop condition detected [Legend] 0-state retained 1-state retained —: Previous state retained ↓...
Page 576 Section 18 I C Bus Interface (IIC) Table 18.6 Flags and Transfer States (Slave Mode) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State — Idle state (flag clearing required) 1↑ 0↓ — 1↑ Start condition detected 1↑/0 — 1↑...
Page 577: C Bus Status Register (Icsr)
Section 18 I C Bus Interface (IIC) 18.3.6 C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 18.5 and 18.6. Initial Bit Name Value Description ESTP R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode.
Page 578 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description AASX R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Page 579 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Page 580 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description Acknowledge Bit ACKB Stores acknowledge data. The bit function varies depending on transmit mode and receive mode. Transmit mode: Holds the acknowledge data returned by the receiving device. [Setting condition] When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode...
Page 581: C Bus Control Initialization Register (Icres)
Section 18 I C Bus Interface (IIC) 18.3.7 C Bus Control Initialization Register (ICRES) ICRES controls IIC internal latch clearance. Initial Bit Name Value Description 7 to 5 — All 0 Reserved The initial value should not be changed. — Reserved IIC Clear 3 to 0 CLR3...
Page 582: C Bus Extended Control Register (Icxr)
Section 18 I C Bus Interface (IIC) 18.3.8 C Bus Extended Control Register (ICXR) ICXR enables or disables the I C bus interface interrupt generation and handshake control, and indicates the status of receive/transmit operations. Initial Bit Name Value Description STOPIM Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the...
Page 583 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description ICDRF Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out.
Page 584 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description ICDRE Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has...
Page 585 Section 18 I C Bus Interface (IIC) Initial Bit Name Value Description ALIE Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. ALSL Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
Page 586: Operation
Section 18 I C Bus Interface (IIC) 18.4 Operation The I C bus interface has an I C bus format and a serial format. 18.4.1 C Bus Data Format The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 18.3. The first frame following a start condition always consists of 9 bits.
Page 587 Section 18 I C Bus Interface (IIC) 1–7 1–7 1–7 DATA DATA Figure 18.5 I C Bus Timing Table 18.7 I C Bus Data Format Symbols Legend Start condition. The master device drives SDA from high to low while SCL is high Slave address.
Page 588: Initialization
Section 18 I C Bus Interface (IIC) 18.4.2 Initialization Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) Cancel module stop mode MSTPB4 = 0 (IIC_2) (MSTPCRL, MSTPCRB) Enable the CPU accessing to the IIC control register and data register Set IICE = 1 in STCR...
Page 589 Section 18 I C Bus Interface (IIC) Start Initialize IIC [1] Initialization Read BBSY flag in ICCR [2] Test the status of the SCL and SDA lines. BBSY = 0? Set MST = 1 and [3] Select master transmit mode. TRS = 1 in ICCR Set BBSY =1 and [4] Start condition issuance...
Page 590 Section 18 I C Bus Interface (IIC) The master mode transmission procedure and operations are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3.
Page 591 Section 18 I C Bus Interface (IIC) 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Page 592 Section 18 I C Bus Interface (IIC) Stop condition issuance (master output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (master output) Data 1 Data 2 [10] (slave output) ICDRE IRIC IRTR ICDR...
Page 593: Master Receive Operation
Section 18 I C Bus Interface (IIC) 18.4.4 Master Receive Operation In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation.
Page 594 Section 18 I C Bus Interface (IIC) The master mode reception procedure and operations are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0 to determine the end of reception.
Page 595 Section 18 I C Bus Interface (IIC) Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 596: Slave Receive Operation
Section 18 I C Bus Interface (IIC) 18.4.5 Slave Receive Operation In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address.
Page 597 Section 18 I C Bus Interface (IIC) Slave receive mode [1] Initialization. Select slave receive mode. Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Clear IRIC flag in ICCR ICDRF = 1? [2] Read the receive data remaining unread.
Page 598 Section 18 I C Bus Interface (IIC) The slave mode reception procedure and operations are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
Page 599 Section 18 I C Bus Interface (IIC) Start condition generation [7] SCL is fixed low until ICDR is read (Pin waveform) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output) Slave address...
Page 600: Slave Transmit Operation
Section 18 I C Bus Interface (IIC) 18.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode.
Page 601 Section 18 I C Bus Interface (IIC) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1.
Page 602 Section 18 I C Bus Interface (IIC) 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9.
Page 603: Iric Setting Timing And Scl Control
Section 18 I C Bus Interface (IIC) 18.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock.
Page 604 Section 18 I C Bus Interface (IIC) When WAIT = 1, and FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC Clear IRIC Clear IRIC User processing (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. IRIC User processing Write to ICDR (transmit)
Page 605: Noise Canceler
Section 18 I C Bus Interface (IIC) 18.4.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18.21 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 606 Section 18 I C Bus Interface (IIC) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags) • Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR •...
Page 607: Interrupt Sources
Section 18 I C Bus Interface (IIC) 18.5 Interrupt Sources The IIC has interrupt source IICI. Table 18.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the interrupt controller independently.
Page 608: Usage Notes
Section 18 I C Bus Interface (IIC) 18.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I C bus, neither condition will be output correctly.
Page 609 Section 18 I C Bus Interface (IIC) 4. The I C bus interface specification for the SCL rise time t is 1000 ns or less (300 ns for high- speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication.
Page 610 Section 18 I C Bus Interface (IIC) Table 18.11 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus φ = φ = φ = φ = Influence Specification Item Indication (Max.) (Min.) 8 MHz 10 MHz...
Page 611: Module Stop Mode Setting
Section 18 I C Bus Interface (IIC) 6. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly.
Page 612 Section 18 I C Bus Interface (IIC) Rev. 1.00 Apr. 28, 2008 Page 586 of 994 REJ09B0452-0100...
Page 613: Section 19 Keyboard Buffer Control Unit (Ps2)
Section 19 Keyboard Buffer Control Unit (PS2) Section 19 Keyboard Buffer Control Unit (PS2) This LSI has four on-chip keyboard buffer control unit (PS2) channels. The PS2 is provided with functions conforming to the PS/2 interface specifications. Data transfer using the PS2 employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc.
Page 614 Section 19 Keyboard Buffer Control Unit (PS2) Internal data bus KBBR KBTR Transmission start KBCR1 (PS2AD, PS2BD, KCLKI KBCRH Control PS2CD, logic PS2DD) Parity KCLK Transmit counter (PS2AC, nalue KBCR2 PS2BC, PS2CC, KBCRL KCLKO PS2DC) Register counter value KBI interrupt KCI interrupt KTI interrupt [Legend]...
Page 615: Input/Output Pins
Section 19 Keyboard Buffer Control Unit (PS2) Figure 19.2 shows how the PS2 is connected. System side Keyboard side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer control unit (This LSI) Figure 19.2 PS2 Connection 19.2...
Page 616: Register Descriptions
Section 19 Keyboard Buffer Control Unit (PS2) 19.3 Register Descriptions The PS2 has the following registers for each channel. Table 19.2 Register Configuration Initial Data Bus Channel Register Name Abbreviation Value Address Width Channel 0 Keyboard control register 1_0 KBCR1_0 H'00 H'FEC0 8 Keyboard control register 2_0...
Page 617: Keyboard Control Register 1 (Kbcr1)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.1 Keyboard Control Register 1 (KBCR1) KBCR1 controls data transmission and interrupt, selects parity, and detects transmit error. Initial Bit Name Value Description KBTS Transmit Start Selects start of data transmission or disables transmission.
Page 618 Section 19 Keyboard Buffer Control Unit (PS2) Initial Bit Name Value Description KCIF R/(W)* First KCLK Falling Interrupt Flag Indicates that the first falling edge of KCLK is detected. When KCIE and KCIF are set to 1, requests the CPU an interrupt.
Page 619: Keyboard Buffer Control Register 2 (Kbcr2)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.2 Keyboard Buffer Control Register 2 (KBCR2) KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK. Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD (LSB-first).
Page 620: Keyboard Control Register H (Kbcrh)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.3 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer control unit. Initial Bit Name Value Description KBIOE Keyboard In/Out Enable Selects whether or not the keyboard buffer control unit is used.
Page 621 Section 19 Keyboard Buffer Control Unit (PS2) Initial Bit Name Value Description R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR. When both KBIE and KBF are set to1, an interrupt request is sent to the CPU.
Page 622: Keyboard Control Register L (Kbcrl)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.4 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer control unit pin output. Initial Bit Name Value Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled KCLKO...
Page 623 Section 19 Keyboard Buffer Control Unit (PS2) Initial Bit Name Value Description RXCR3 Receive Counter RXCR2 These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be RXCR1 modified. RXCR0 The receive counter is initialized by a reset and when 0 is written in KBE.
Page 624: Keyboard Data Buffer Register (Kbbr)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.5 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Initial Bit Name Value Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset or when KBIOE is cleared to 0.
Page 625: Operation
Section 19 Keyboard Buffer Control Unit (PS2) 19.4 Operation 19.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 626 Section 19 Keyboard Buffer Control Unit (PS2) Flag cleared Receive processing/ error handling KCLK (pin state) Start Parity bit Stop bit (pin state) KCLK (input) KCLK Automatic I/O inhibit (output) KB7 to KB0 Previous data Receive data [1] [2] [3] [4] [5] Figure 19.4 Receive Timing Rev.
Page 627: Transmit Operation
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 628: Receive Abort
Section 19 Keyboard Buffer Control Unit (PS2) I/O inhibit KCLK (pin state) Receive Start bit completed Parity Stop bit notification (pin state) KCLK (input) I/O inhibit KCLK (output) KBTE KTER KBTS [9] [10] [11] [6] [7] [8] [1] to [3] Figure 19.6 Transmit Timing 19.4.3 Receive Abort...
Page 629 Section 19 Keyboard Buffer Control Unit (PS2) [1] Read KBCRL, and if KBF = 1, perform processing 1. Start [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less Receive state than B'1001, write 0 in KCLKO to abort reception.
Page 630 Section 19 Keyboard Buffer Control Unit (PS2) Processing 1 [1] On the system side, drive the KCLK pin low, setting Receive operation ends the I/O inhibit state. normally Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted.
Page 631: Kclki And Kdi Read Timing
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.4 KCLKI and KDI Read Timing Figure 19.9 shows the KCLKI and KDI read timing. φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.9 KCLKI and KDI Read Timing 19.4.5 KCLKO and KDO Write Timing...
Page 632: Kbf Setting Timing And Kclk Control
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.6 KBF Setting Timing and KCLK Control Figure 19.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK 11th fall (pin) Internal KCLK Falling edge signal RXCR3 to B'1010 B'0000 RXCR0 KCLK Automatic I/O inhibit...
Page 633: Receive Timing
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.7 Receive Timing Figure 19.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to N + 1 N + 2 RXCR0 Internal KD (KDI) KBBR7 to KBBR0 Note: * φ...
Page 634: Kclk Fall Interrupt Operation
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.9 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRH to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 19.14 shows the setting method and an example of operation.
Page 635: 19.4.10 First Kclk Falling Interrupt
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.10 First KCLK Falling Interrupt An interrupt can be generated by detecting the first falling edge of KCLK on reception and transmission. Software standby mode and watch mode can be cancelled by a first KCLK falling interrupt.
Page 636 Section 19 Keyboard Buffer Control Unit (PS2) • Canceling software standby mode and watch mode Software standby mode and watch mode are cancelled by a first KCLK falling interrupt. In this case, an interrupt is generated at the first KCLK since software standby mode or watch mode has been shifted (figure 19.17).
Page 637 Section 19 Keyboard Buffer Control Unit (PS2) Software standby mode and watch mode Interrupt control block Falling edge detection circuit Interrupt KCLK Interrupt request vector to CPU generation circuit Interrupt control Figure 19.16 First KCLK Interrupt Path (a) Interrupt timing in software standby mode and watch mode KCLK Software standby mode and watch mode...
Page 638 Section 19 Keyboard Buffer Control Unit (PS2) KCLK First KCLK falling edge Automatic clear Internal flag Interrupt generated Interrupt accepted (Accepted at any timing) Figure 19.18 Internal Flag of First KCLK Falling Interrupt in Software Standby Mode and Watch Mode Rev.
Page 639: Usage Notes
Section 19 Keyboard Buffer Control Unit (PS2) 19.5 Usage Notes 19.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected.
Page 640: Kd Output By Kdo Bit (Kbcrl) And By Automatic Transmission
Section 19 Keyboard Buffer Control Unit (PS2) 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission Figure 19.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the automatic transmission. Switch to the KD output by the automatic transmission is performed when KBTS is set to 1 and TXCR is not cleared to 0.
Page 641: Section 20 Lpc Interface (Lpc)
Section 20 LPC Interface (LPC) Section 20 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC includes four register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock.
Page 642 Section 20 LPC Interface (LPC) Figure 20.1 shows a block diagram of the LPC. Module data bus Parallel → serial conversion TWR0MW IDR4 SERIRQ IDR3 TWR1 to TWR15 IDR2 IDR1 SIRQCR0 to 4 CLKRUN HISEL Cycle detection LPCPD Control logic Serial →...
Page 643: Input/Output Pins
Section 20 LPC Interface (LPC) 20.2 Input/Output Pins Table 20.1 lists the LPC pin configuration. Table 20.1 Pin Configuration Name Abbreviation Port Function LPC address/ LAD3 to LAD0 P33 to P30 I/O Cycle type/address/data signals data 3 to 0 serially (4-signal-line) transferred in synchronization with LCLK LFRAME LPC frame...
Page 644: Register Descriptions
Section 20 LPC Interface (LPC) 20.3 Register Descriptions The LPC has the following registers. Table 20.2 Register Configuration Initial Data Bus Register Name Abbreviation Slave Host Value Address Width  Host interface control register 0 HICR0 H'00 H'FE40  Host interface control register 1 HICR1 H'00 H'FE41...
Page 645 Section 20 LPC Interface (LPC) Initial Data Bus Register Name Abbreviation Slave Host Value Address Width Bidirectional data register 0MW TWR0MW H'00 H'FE20 Bidirectional data register 0SW TWR0SW H'00 H'FE20 Bidirectional data register 1 TWR1 H'00 H'FE21 Bidirectional data register 2 TWR2 H'00 H'FE22...
Page 646: Host Interface Control Registers 0 And 1 (Hicr0 And Hicr1)
Section 20 LPC Interface (LPC) 20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface.
Page 647 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  FGA20E Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. When the fast Gate A20 is disabled, the normal Gate A20 can be implemented by firmware controlling P81 output.
Page 648 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  PMEE PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed. PMEE PMEB : PME output disabled, other function...
Page 649 Section 20 LPC Interface (LPC) • HICR1 Initial Bit Name Value Slave Host Description  LPCBSY LPC Busy Indicates that the LPC interface is processing a transfer cycle. 0: LPC interface is in transfer cycle wait state • Bus idle, or transfer cycle not subject to processing is in progress •...
Page 650 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  IRQBSY SERIRQ Busy Indicates that the LPC interface's SERIRQ is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] • LPC hardware reset or LPC software reset •...
Page 651 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  SDWNB LPC Software Shutdown Bit Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 20.4.4, LPC Interface Shutdown Function (LPCPD).
Page 652: Host Interface Control Registers 2 And 3 (Hicr2 And Hicr3)
Section 20 LPC Interface (LPC) 20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3) HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 and the bit 7 in HICR2 monitor the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits are decided by the pin states.
Page 653 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description R/(W)*  ABRT LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] •...
Page 654 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  IBFIE1 IDR1 Receive Complete interrupt Enable Enables or disables IBFI1 interrupt to the slave (this LSI). 0: Input data register (IDR1) receive complete interrupt requests disabled 1: Input data register (IDR1) receive complete interrupt requests enabled ...
Page 655: Host Interface Control Register 4 (Hicr4)
Section 20 LPC Interface (LPC) 20.3.3 Host Interface Control Register 4 (HICR4) HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface slave (this LSI). Initial Bit Name Value Slave Host Description   Reserved The initial value bit should not be changed.
Page 656: Host Interface Control Register 5 (Hicr5)
Section 20 LPC Interface (LPC) 20.3.4 Host Interface Control Register 5 (HICR5) HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts. Initial Bit Name Value Slave Host Description  OBEIE Output Buffer Empty Interrupt Enable Enables or disables OBEI interrupts (for this LSI).
Page 657: Lpc Channel 1 Address Registers H And L (Ladr1H And Ladr1L)
Section 20 LPC Interface (LPC) 20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L) LADR1 sets the LPC channel 1 host address. The LADR1 contents must not be changed while channel 1 is operating (while LPC1E is set to 1). •...
Page 658: Lpc Channel 2 Address Registers H And L (Ladr2H And Ladr2L)
Section 20 LPC Interface (LPC) • Host select register I/O Address Transfer Cycle Bits 5 to 3 Bit 2 Bits 1 and 0 Host Select Register Bits 15 to 3 in LADR1 Bits 1 and 0 in LADR1 I/O write IDR1 write (data) Bits 15 to 3 in LADR1 Bits 1 and 0 in LADR1...
Page 659 Section 20 LPC Interface (LPC) • LADR2L Initial Value Bit Name Slave Host Description  Bit 7 Channel 2 Address Bits 7 to 3  Bit 6 Set the LPC channel 2 host address.  Bit 5  Bit 4 ...
Page 660: Lpc Channel 3 Address Registers H And L (Ladr3H And Ladr3L)
Section 20 LPC Interface (LPC) 20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L) LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data registers. The contents of the address fields in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Page 661 Section 20 LPC Interface (LPC) When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored.
Page 662: Lpc Channel 4 Address Registers H And L (Ladr4H And Ladr4L)
Section 20 LPC Interface (LPC) 20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L) LADR4 sets the LPC channel 4 host address. The LADR4 contents must not be changed while channel 4 is operating (while LPC4E is set to 1). •...
Page 663: Input Data Registers 1 To 4 (Idr1 To Idr4)
Section 20 LPC Interface (LPC) • Host select register I/O Address Transfer Bits 5 to 3 Bit 2 Bits 1 and 0 Cycle Host Select Register Bits 15 to 3 in LADR4 Bits 1 and 0 in LADR4 I/O write IDR4 write (data) Bits 15 to 3 in LADR4 Bits 1 and 0 in LADR4...
Page 664: Bidirectional Data Registers 0 To 15 (Twr0 To Twr15)
Section 20 LPC Interface (LPC) 20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave (this LSI) and host. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host and the slave addresses.
Page 665 Section 20 LPC Interface (LPC) • STR1 Bit Name Initial Value Slave Host Description DBU17 Defined by User DBU16 The user can use these bits as necessary. DBU15 DBU14 C/D1 Command/Data When the host writes to IDR1, bit 2 of the I/O address is written into this bit to indicate whether IDR1 contains data or a command.
Page 666 Section 20 LPC Interface (LPC) • STR2 Bit Name Initial Value Slave Host Description DBU27 Defined by User DBU26 The user can use these bits as necessary. DBU25 DBU24 C/D2 Command/Data When the host writes to IDR2, bit 2 of the I/O address is written into this bit to indicate whether IDR2 contains data or a command.
Page 667 Section 20 LPC Interface (LPC) • STR3 (TWRE = 1 or SELSTR3 = 0) Bit Name Initial Value Slave Host Description IBF3B Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition]...
Page 668 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description C/D3 Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command...
Page 669 Section 20 LPC Interface (LPC) • STR3 (TWRE = 0 and SELSTR3 = 1) Bit Name Initial Value Slave Host Description DBU37 Defined by User DBU36 The user can use these bits as necessary. DBU35 DBU34 C/D3 Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command.
Page 670 Section 20 LPC Interface (LPC) • STR4 Bit Name Initial Value Slave Host Description DBU47 Defined by User DBU46 The user can use these bits as necessary. DBU45 DBU44 C/D4 Command/Data Flag When the host writes to IDR4, bit 2 of the I/O address is written into this bit to indicate whether IDR4 contains data or a command.
Page 671: Serirq Control Register 0 (Sirqcr0)
Section 20 LPC Interface (LPC) 20.3.13 SERIRQ Control Register 0 (SIRQCR0) SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. Bit Name Initial Value Slave Host Description  Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame).
Page 672 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE3B Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] •...
Page 673 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE2 Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] •...
Page 674 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ1E1 Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] •...
Page 675: Serirq Control Register 1 (Sirqcr1)
Section 20 LPC Interface (LPC) 20.3.14 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. Bit Name Initial Value Slave Host Description  Host IRQ11 Interrupt Enable 3 IRQ11E3 0 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write.
Page 676 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E3 Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQE9E3 is disabled [Clearing conditions] •...
Page 677 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ11E2 0 Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQE11E2 is disabled [Clearing conditions] •...
Page 678 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E2 Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQE9E2 is disabled [Clearing conditions] •...
Page 679: Serirq Control Register 2 (Sirqcr2)
Section 20 LPC Interface (LPC) 20.3.15 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs. Bit Name Initial Value Slave Host Description  IEDIR3 Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable...
Page 680 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ11E4 0 Host IRQ11 Interrupt Enable 4 Enables or disables an HIRQ11 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ11 interrupt request by OBF4 and IRQE11E4 is disabled [Clearing conditions] •...
Page 681 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E4 Host IRQ9 Interrupt Enable 4 Enables or disables an HIRQ9 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ9 interrupt request by OBF4 and IRQE9E4 is disabled [Clearing conditions] •...
Page 682: Serirq Control Register 3 (Sirqcr3)
Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE4 Host SMI Interrupt Enable 4 Enables or disables an SMI interrupt request when OBF4 is set by an ODR4 write. 0: Host SMI interrupt request by OBF4 and SMIE4 is disabled [Clearing conditions] •...
Page 683: Serirq Control Register 4 (Sirqcr4)
Section 20 LPC Interface (LPC) 20.3.17 SERIRQ Control Register 4 (SIRQCR4) SIRQCR4 is used to select the SERIRQ interrupt requests of the SCIF. Initial Bit Name Value Slave Host Description 7 to 4   All 0 Reserved The initial value should not be changed. ...
Page 684: Scif Address Register (Scifadrh, Scifadrl)
Section 20 LPC Interface (LPC) 20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) SCIFADR sets the host addresses of the SCIF. Do not change the contents of SCIFADR during operation of the SCIF (i.e. while SCIFE is set to 1). • SCIFADRH Initial Bit Name Value...
Page 685: Host Interface Select Register (Hisel)
Section 20 LPC Interface (LPC) 20.3.19 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame. Initial Bit Name Value Slave Host Description ...
Page 686: Operation
Section 20 LPC Interface (LPC) 20.4 Operation 20.4.1 LPC interface Activation The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in HICR0 and LPC4E in HICR4. When the LPC interface is activated, the related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins.
Page 687: Lpc I/O Cycles
Section 20 LPC Interface (LPC) 20.4.2 LPC I/O Cycles There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, bus master I/O write, FW memory read, and FW memory write.
Page 688 Section 20 LPC Interface (LPC) Table 20.3 LPC I/O Cycle I/O Read Cycle I/O Write Cycle State Drive Value Drive Value Count Contents Source (3 to 0) Contents Source (3 to 0) Start Host 0000 Start Host 0000 Cycle type/direction Host 0000 Cycle type/direction...
Page 689 Section 20 LPC Interface (LPC) LCLK LFRAME LAD3 to Start ADDR Sync Data Start LAD0 Cycle type, direction, and size Number of clocks Figure 20.2 Typical LFRAME Timing LCLK LFRAME Start ADDR Sync LAD3 to LAD0 Master will drive high Cycle type, Slave must stop driving direction,...
Page 690: Gate A20
Section 20 LPC Interface (LPC) 20.4.3 Gate A20 The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0.
Page 691 Section 20 LPC Interface (LPC) Table 20.4 GA20 Setting/Clearing Timing Pin Name Setting Condition Clearing Condition GA20 When bit 1 of the data that follows an When bit 1 of the data that follows an H'D1 host command is 1 H'D1 host command is 0 Start Host write...
Page 692 Section 20 LPC Interface (LPC) Table 20.5 Fast Gate A20 Output Signals Internal CPU Interrupt Flag GA20 C/D1 Data/Command (IBF) (P81) Remarks H'D1 command Turn-on sequence 1 data* H'FF command Q (1) H'D1 command Turn-off sequence 0 data* H'FF command Q (0) H'D1 command Turn-on sequence...
Page 693: Lpc Interface Shutdown Function (Lpcpd)
Section 20 LPC Interface (LPC) 20.4.4 LPC Interface Shutdown Function (LPCPD) The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown.
Page 694 Section 20 LPC Interface (LPC) Table 20.6 shows the scope of the LPC interface pin shutdown. Table 20.6 Scope of LPC Interface Pin Shutdown Scope of Abbreviation Port Shutdown Notes LAD3 to LAD0 P33 to P30 Hi-Z LFRAME Input Hi-Z LRESET Input LPC hardware reset function is active...
Page 695 Section 20 LPC Interface (LPC) Table 20.7 Scope of Initialization in Each LPC interface Mode System Items Initialized Reset LPC Reset Shutdown LPC transfer cycle sequencer (internal state), LPCBSY and ABRT Initialized Initialized Initialized flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and Initialized Initialized Initialized...
Page 696 Section 20 LPC Interface (LPC) Figure 20.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3 to LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 20.5 Power-Down State Termination Timing Rev.
Page 697: Lpc Interface Serialized Interrupt Operation (Serirq)
Section 20 LPC Interface (LPC) 20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt.
Page 698 Section 20 LPC Interface (LPC) Table 20.8 Serialized Interrupt Transfer Cycle Frame Configuration Serial Interrupt Transfer Cycle Frame Drive Number Count Contents Source of States Notes Start Slave In quiet mode only, slave drive possible in first Host state, then next 3 states 0-driven by host IRQ0 Slave IRQ1...
Page 699: Lpc Interface Clock Start Request
Section 20 LPC Interface (LPC) There are two modescontinuous mode and quiet modefor serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals.
Page 700: Interrupt Sources
Section 20 LPC Interface (LPC) 20.5 Interrupt Sources 20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI The host has six interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, OBEI, and ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively.
Page 701: Smi, Hirq1, Hirq3, Hirq4, Hirq5, Hirq6, Hirq7, Hirq8, Hirq9
Section 20 LPC Interface (LPC) 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 and the SCIF, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2, 3, 4 or SCIF.
Page 702 Section 20 LPC Interface (LPC) Table 20.10 HIRQ Setting and Clearing Conditions when LPC Channels are Used Host Interrupt Setting Condition Clearing Condition HIRQ1 Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit IRQ1E1, from bit IRQ1E1 and writes 1 or host reads ODR1 HIRQ12 Internal CPU writes to ODR1, then reads 0...
Page 703 Section 20 LPC Interface (LPC) Table 20.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used Host Interrupt Setting Condition Clearing Condition HIRQi Internal CPU sets the corresponding Reads FMSR and clears the DDCD (i = 1 to 15) SERIRQ host interrupt request for the bit in FMSR SCIF in SIRQCR4 (for details, see the...
Page 704: Usage Note
Section 20 LPC Interface (LPC) 20.6 Usage Note 20.6.1 Data Conflict The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted.
Page 705 Section 20 LPC Interface (LPC) Table 20.12 Host Address Example Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 IDR3 H'A24A and H'A24E H'3FD0 and H'3FD4 ODR3 H'A24A H'3FD0 STR3 H'A24E H'3FD4 TWR0MW H'A250 H'3FC0 TWR0SW H'A250 H'3FC0 TWR1...
Page 706 Section 20 LPC Interface (LPC) Rev. 1.00 Apr. 28, 2008 Page 680 of 994 REJ09B0452-0100...
Page 707: Section 21 Fsi Interface
Section 21 FSI Interface Section 21 FSI Interface This LSI incorporates the SPI flash memory serial interface (FSI) that supports the communication between this LSI and SPI flash memory. The FSI performs communications using the LPC or CPU of this LSI as a master. 21.1 Features Figure 21.1 shows a block diagram of the FSI.
Page 708 Section 21 FSI Interface FSICMDI, FSIWI FSITEI, FSIRXI FSICR1/2 FSIINS FSIBNR SLCR FSIRDINS FSISTR FSIPPINS FSIHBARH/L FSISR LCLK Address-Change FSISS LAD 3 to 0 Trans/Rev LFRAME FSICK CMDHBRH/L Controller FSILSTR1/2 FSIGPR1 to F FSIARLH/M/L FSIWDHH/HL/LH/LL FSITDR FSIRDR 0 to 7 FSICMDR FSIDO FSISFR...
Page 709: Input/Output Pins
Section 21 FSI Interface 21.2 Input/Output Pins Table 21.1 shows the input/output pins of the FSI. Table 21.1 Pin Configuration Pin Name Symbol Function FSI slave select FSISS Output FSI slave select signal FSI clock FSICK Output FSI clock signal FSI master data input FSIDI Input...
Page 710: Register Description
Section 21 FSI Interface 21.3 Register Description The FSI consists of the following registers. Table 21.3 List of Register Addresses Initial Register Name Abbreviation Host Value Address  FSI control register 1 FSICR1 H'00 H'FC90  FSI control register 2 FSICR2 H'00 H'FC91...
Page 711 Section 21 FSI Interface Initial Register Name Abbreviation Host Value Address FSI general-purpose register 1 FSIGPR1 H'00 H'FC57 FSI general-purpose register 2 FSIGPR2 H'00 H'FC58 FSI general-purpose register 3 FSIGPR3 H'00 H'FC59 FSI general-purpose register 4 FSIGPR4 H'00 H'FC5A FSI general-purpose register 5 FSIGPR5 H'00 H'FC5B...
Page 712: Fsi Control Register 1 (Fsicr1)
Section 21 FSI Interface 21.3.1 FSI Control Register 1 (FSICR1) The FSICR1 control bits are classified into three functionalities: resetting the FSI internal signals, enabling/disabling FSI functions, and selecting FSI functions. Initial Bit Name Value Host Description  SRES Software Reset Controls initialization of the FSI internal sequencer.
Page 713 Section 21 FSI Interface Initial Bit Name Value Host Description  CPHS CPHS: Selects the polarity of the FSICK clock.  CPOS CPOS: Selects the phase of the FSICK clock. CPHS CPOS Initial value of FSICK: Low level Data changes at the FSICK falling edge.
Page 714: Fsi Control Register 2 (Fsicr2)
Section 21 FSI Interface 21.3.2 FSI Control Register 2 (FSICR2) The FSICR2 control bits are classified into two functionalities: enabling/disabling the FSI communications and enabling/disabling the FSI internal interrupts. Initial Bit Name Value Host Description  FSI Transmit Enable Controls FSI transmission and indicates transmission status in combination with the LFBUSY bit.
Page 715: Fsi Byte Count Register (Fsibnr)
Section 21 FSI Interface 21.3.3 FSI Byte Count Register (FSIBNR) The FSIBNR sets the number of bytes to be transmitted or received by the FSI. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing. Initial Bit Name Value...
Page 716: Fsi Instruction Register (Fsiins)
Section 21 FSI Interface Initial Bit Name Value Host Description  2 to 0 RBN2 Receive Byte Count 2-0 RBN1 These bits specify the number of data bytes to be received. After the FSI reception operation ends RBN0 (when FSIRXI in FSISTR is 1), the RBN value is decremented (−1) each time FSIRDR is read.
Page 717: Fsi Instruction Register (Fsirdins)
Section 21 FSI Interface 21.3.5 FSI Instruction Register (FSIRDINS) FSIRDINS sets a read operation instruction to be sent to FSITDR during read operation. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should be modified during initialization.
Page 718 Section 21 FSI Interface Initial Bit Name Value Host Description  Transmit Data Register Full Indicates whether or not there is data to be written by the EC (this LSI). 0: There is no write data. [Clearing condition] When write data transmission to the SPI flash memory is completed.
Page 719: Fsi Transmit Data Registers 0 To 7 (Fsitdr0 To Fsitdr7)
Section 21 FSI Interface 21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7) FSITDR stores a total of 8 bytes of transmit data. A total of 8 bytes of addresses, instructions, and data items can be transferred continuously from FSITDR0 through FSITDR7 in this order to the SPI flash memory.
Page 720: Fsi Access Host Base Address Registers H And L (Fsihbarh And Fsihbarl)
Section 21 FSI Interface 21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL) FSIHBARH and FSIHBARL store the upper 16 bits of the host start address which is necessary to convert the host address to the SPI flash memory address. The input range of the host address will be determined based on the host start address set in these registers and the memory size set in FSISR.
Page 721: Fsi Command Host Base Address Registers H And L
Section 21 FSI Interface Initial Bit Name Value Host Description 7 to 2   All 0 Reserved The initial value should not be changed.  FSIMS1 These bits specify the SPI flash memory size.  FSIMS0 00: 1 MB 01: 2 MB 10: 4 MB 11: 8 MB...
Page 722: Fsi Command Register (Fsicmdr)
Section 21 FSI Interface 21.3.13 FSI Command Register (FSICMDR) FSICMDR stores command data during FSI command reception. FSICMDR stores command data when the FSICMDI bit in FSILSTR1 is cleared to 0. It does not store command data when the FSICMDI bit is set to 1. Initial Bit Name Value...
Page 723 Section 21 FSI Interface Initial Bit Name Value Host Description FSIDMYE FSI Dummy Enable 0: Disables FSI dummy. 1: Enables FSI dummy. FSIWBUSY 0 R/W* R FSI Write Busy Flag 0: FSI write transfer is completed. [Clearing condition] • When this bit is read as 1 and then written with 0. 1: FSI write in transferring [Setting condition] •...
Page 724: Fsi Lpc Command Status Register 2 (Fsilstr2)
Section 21 FSI Interface 21.3.15 FSI LPC Command Status Register 2 (FSILSTR2) FSILSTR2 indicates the LPC internal status. Initial Bit Name Value Host Description 7 to 5   All 0 Reserved The initial value should not be modified.  FSIDWBUSY FSI Direct Write Busy Flag Indicates a FSI write transfer status during LPC-...
Page 725: Fsi General-Purpose Registers 1 To F (Fsigpr1 To Fsigprf)
Section 21 FSI Interface 21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) FSIGPR1 to FSIGPRF store data such as the result of FSI command interrupt processing. • FSIGPR1 to FSIGPRF Initial Bit Name Value Host Description 7 to 0 bit 7 to bit 0 All 0 These bits store results of FSI command interrupt processing.
Page 726: Fsi Address Registers H, M, And L (Fsiarh, Fsiarm, And Fsiarl)
Section 21 FSI Interface Initial Bit Name Value Host Description  FLDCT FSI LPC Direct Selects access mode in SPI flash memory write. For details, see section 21.4.6, SPI Flash Memory Write Operation Mode. 0: LPC-SPI indirect transfer 1: LPC-SPI direct transfer ...
Page 727: Fsi Write Data Registers Hh, Hl, Lh, And Ll
Section 21 FSI Interface • FSIARL Initial Bit Name Value Host Description  7 to 0 bit 7 to bit 0 All 0 These bits store bits [7:0] of the SPI flash memory address. 21.3.19 FSI Write Data Registers HH, HL, LH, and LL (FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL) FSIWDR stores data to be written to the SPI flash memory.
Page 728 Section 21 FSI Interface • FSIWDRLH Initial Bit Name Value Host Description  7 to 0 bit 15 to All 0 These bits store bits [15:8] of the SPI flash memory bit 8 write data. • FSIWDRLL Initial Bit Name Value Host Description ...
Page 729: Operation
Section 21 FSI Interface 21.4 Operation 21.4.1 LPC/FW Memory Cycles In LPC/FW memory read and write cycles, data is transferred using LAD3 to LAD0 synchronously with LCLK. The order of data transfer is shown in table 21.4. In a cycle returning synchronization signal from the slave, the slave usually returns B'1010 to notify the host of error occurrence;...
Page 730 Section 21 FSI Interface LPC Memory Read Cycles LPC Memory Write Cycles State Counts Content Driven by Value (3 to 0) Content Driven by Value (3 to 0) Slave 0000 Turn-around None ZZZZ Synchronization Data 1 Slave bit 3 to bit 0 Wait* Slave 0110...
Page 731: Spi Flash Memory Transfer
Section 21 FSI Interface FW Memory Read Cycles FW Memory Write Cycles State Counts Content Driven by Value (3 to 0) Content Driven by Value (3 to 0) Turn-around Slave 1111 Turn-around Slave 1111 (recovery) (recovery) Turn-around None ZZZZ Turn-around None ZZZZ Note:...
Page 732: Flash Memory Instructions
Section 21 FSI Interface 21.4.3 Flash Memory Instructions Table 21.6 lists the flash memory instructions (INS). Table 21.6 List of Instructions (INS) Instruction Name Description WREN Sets write-enable WRDI Resets write-enable RDSR Reads status register WRSR Writes status register READ Reads SPI flash memory Fast-Read Fast-reads SPI flash memory...
Page 733: Fsi Memory Cycle (Direct Transfer Between Lpc And Spi)
Section 21 FSI Interface 21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI) The FSI supports direct transfer between the host and SPI flash memory. If the host address input in LPC/FW memory write cycle matches the host address set in FSIHBARH, FSIHBARL, or FSISR, the FSI memory cycle starts.
Page 734 Section 21 FSI Interface Byte/Page-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 and the FSIDMYE bit in FSILSTR1 are cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the SPI flash memory address and write data are stored in FSIAR and FSIWDR, respectively.
Page 735 Section 21 FSI Interface LCLK LFRAME LAD[3:0] ST CT ADDR DATA WAIT SY TAR φ FSIAR[23:0] H'06-4A-70 H'67-45-23-01 FSIWDR[31:0] H'02 FSIPPINS[7:0] FSICR2 TE bit FSITDR7 to H'67-45-23-01-70-4A-06-02 FSITDR0 FSISTR OBF bit FSISS FSICK (CPOS = CPHS = 0) H'02->06->4A->70->01->23->45->67 FSIDO Figure 21.5 Page-Program Instruction Execution Timing Rev.
Page 736 Section 21 FSI Interface AAI-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 is set to 1 and the FSIDMYE bit in FSILSTR1 is cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the flash memory address and write data are stored in FSIAR and FSIWDR, respectively.
Page 737 Section 21 FSI Interface LCLK LFRAME LAD[3:0] ADDR DATA TAR WAIT SY TAR φ FSIAR[23:0] H'06-4A-70 FSIWDR[31:0] H'23 FSICR2 TE bit FSITDR7 to H'23-AF FSITDR0 FSISTR OBF bit FSISS FSICK (CPOS = CPHS =0) FSIDO H'AF->23 Figure 21.7 AAI-Program Instruction Execution Timing (Second and Following Bytes) Read Instructions If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI...
Page 738 Section 21 FSI Interface First receive data H'01 FSIRDR3 Internal register Second receive data H'23 H'67_45_23_01 Third receive data H'45 Fourth receive data H'67 FSIRDR0 FSIAR[23:0] FSIAR[7:0] H'70 FSITDR3 H'06_4A_70 FSIAR[15:8] H'4A FSIAR[23:16] H'06 FSIRDINS[7:0] H'03 H'03 FSITDR0 FSISFR FSIDI FSIDO Figure 21.8 Data Transfer to FSIRDR (Example) LCLK...
Page 739 Section 21 FSI Interface Fast-Read Instruction If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is set to 1, the host address is stored in FSIAR. Then, the SPI flash memory address and the instruction which is stored in FSIRDINS in advance are transferred to FSITDR.
Page 740: Fsi Memory Cycle (Lpc-Spi Command Transfer)
Section 21 FSI Interface 21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer) The FSI supports instructions other than Byte/Page-Program instructions, AAI-Program instruction, Read instruction, and Fast-Read instruction by using an LPC-SPI command transfer. FSI Command Space Specific host address space can be used as FSI command space according to the CMDHBAR settings.
Page 741 Section 21 FSI Interface FSI Command Write If an LPC/FW memory write cycle for the FSI command space occurs, the FSI performs the FSI- FLASH command write operation. Figure 21.12 shows an example of FSI Command write operation. CMDHBAR: H'EFFF H'EFFF_0000 * FSICMDR[7:0] H'EFFF_F000...
Page 742 Section 21 FSI Interface FSI Command Read Figure 21.13 shows an example of FSI command read. CMDHBAR: H'EFFF ∗ H'EFFF_0000 H'EFFF_F000 FSILSTR1 CMD0 CMD1 FSIGPR1 FSIGPR2 to D FSIGPRE CMDE CMDF FSIGPRF H'EFFF_F00F H'EFFF_FFFF Host address Note: * The upper 16 bits of the host address are set to the value in the CMDHBAR register. Figure 21.13 FSI Command Read (Example) As shown in figure 21.13, if a host address ranging from H'EFFF_F000 to H'EFFF_F00F is accessed in LPC/FW memory read cycle while the CMDHBAR register is set to H'EFFF, the...
Page 743 Section 21 FSI Interface FSI Dummy Write Figure 21.14 shows an example of FSI dummy write. FSI Dummy Write FSIHBAR: H'231F FSISR: H'00 (1 MB) FSIDMYE CMDHBAR: H'EFFF FSIWDR[31:0] H'73 H'2325_4A76 H'0000_0073 FSIAR[23:0] Host address H'06_4A76 Byte-Program FSIDMYE SPI Flash memory FSIWDR[31:0] H'232E_1BC3 H'0F_1BC3...
Page 744 Section 21 FSI Interface FSI Command Usage Example 1 (SPI Flash Memory Erasure) The FSI commands enable the execution of several instructions for the SPI flash memory. Figure 21.15 shows an example of executing the SPI flash memory erasure instruction. FSIHBAR: H'231F FSICMDR[7:0] FSISR: H'00 (1 MB)
Page 745 Section 21 FSI Interface STEP1 STEP2 STEP3 φ Cleared by the CPU FSIDMYE Written by the CPU FSICMDI Cleared by the CPU Cleared by the CPU Cleared by the CPU Cleared by the CPU CMDBUSY LPC_ADDR H'EFFF_F000 H'2325_4A76 H'EFFF_F000 FSIAR[23:0] H'06_4A76 Automatically cleared Written by the CPU...
Page 746 Section 21 FSI Interface 4. Execute the SPI flash memory erasure instruction.  Set the TE bit in FSICR2 to 1.  Set the TBN bit in FSIBNR to 4-byte transfer.  Write the FSI address stored in FSIAR to FSITDR1 to FSITDR3. ...
Page 747 Section 21 FSI Interface Step 1: 1. Write a status read setting command (Host). 2. Generate an FSICMDI interrupt request. 3. Clear the FSICMDI bit in FSILSTR1 to 0. 4. Check that the CMDBUSY bit in FSILSTR1 is set to 1 and that the FSICMDI bit in FSILSTR1 is cleared to 0 (Host).
Page 748: Spi Flash Memory Write Operation Mode
Section 21 FSI Interface 21.4.6 SPI Flash Memory Write Operation Mode The write operation to the SPI flash memory in the LPC/FW memory write cycles can be classified into the following four operation modes, depending or the state of FLDCT and FLWAIT.
Page 749: Reset Conditions
Section 21 FSI Interface 21.5 Reset Conditions The FSI supports the LPC shut-down mode. The range of initialization in each mode is shown in table 21.8. Table 21.8 Range of Initialization of FSI in Each Mode System Register Name Reset LPC Reset Shutdown LPC Abort...
Page 750 Section 21 FSI Interface System Register Name Reset LPC Reset Shutdown LPC Abort FSI Reset FSICR1 Bits 7 to 0 Initialized Retained Retained Retained Retained FSICR2 Bits 7 and 6 Initialized Retained Retained Retained Initialized Bits 5 to 0 Initialized Retained Retained Retained...
Page 751: Interrupt Sources
Section 21 FSI Interface 21.6 Interrupt Sources The FSI has four interrupt sources for the slave (this LSI): FSITEI, FSIRXI, FSICMDI, and FSIWI. FSITEI is a transmit end interrupt when the slave executes the SPI flash memory write transfer. FSIRXI is a receive end interrupt when the slave executes the SPI flash memory read transfer.
Page 752 Section 21 FSI Interface Rev. 1.00 Apr. 28, 2008 Page 726 of 994 REJ09B0452-0100...
Page 753: Section 22 A/D Converter
Section 22 A/D Converter Section 22 A/D Converter This LSI includes one unit (unit 0) of successive-approximation-type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. Figure 22.1 shows a block diagram for unit 0. 22.1 Features •...
Page 754 Section 22 A/D Converter Internal Module data bus data bus 10-bit D/A φ – φ/2 φ/4 Control circuit Comparator φ/8 Sample-and- hold circuit AN10 AN11 AN12 AN13 AN14 ADI interrupt AN15 signal Conversion start trigger from TPU or 8-bit timer [Legend] ADCR: A/D control register...
Page 755: Input/Output Pins
Section 22 A/D Converter 22.2 Input/Output Pins Table 22.1 summarizes the pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The AVref pin is a reference voltage pin for the A/D converter. The sixteen analog input pins are divided into two channel sets: analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0 and analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1.
Page 756: Register Descriptions
Section 22 A/D Converter 22.3 Register Descriptions The A/D converter has the following registers. Table 22.2 Register Configuration Data Bus Register Name Abbreviation Initial Value Address Width A/D data register A ADDRA H'0000 H'FC00 A/D data register B ADDRB H'0000 H'FC02 A/D data register C ADDRC...
Page 757: A/D Data Registers A To H (Addra To Addrh)
Section 22 A/D Converter 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers which store a conversion result for each channel are shown in table 22.3.
Page 758: A/D Control/Status Register (Adcsr)
Section 22 A/D Converter 22.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D converter operation. Bit Name Initial Value R/W Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode •...
Page 759 Section 22 A/D Converter Bit Name Initial Value R/W Description Channel Select 3 to 0 Select analog input channels with the SCANE and SCANS bits in ADCRS. The input channel setting must be made when conversion is halted (ADST = 0). When SCANE = 0 When SCANE = 1 When SCANE = 1...
Page 760: A/D Control Register (Adcr)
Section 22 A/D Converter 22.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Name Initial Value R/W Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 Enable the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by conversion trigger from TPU 10: A/D conversion start by conversion trigger from TMR...
Page 761: Operation
Section 22 A/D Converter 22.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. First, select the clock used in A/D conversion. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion.
Page 762: Scan Mode
Section 22 A/D Converter 22.4.2 Scan Mode In scan mode, A/D conversion is performed sequentially on the specified channels (max. four channels or eight channels). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software, the TPU, or the TMR, A/D conversion starts on the first channel in the selected channel set.
Page 763: Input Sampling And A/D Conversion Time
Section 22 A/D Converter 22.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion.
Page 764 Section 22 A/D Converter Table 22.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. ...
Page 765: Interrupt Source
Section 22 A/D Converter 22.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. If the ADF bit in ADCSR has been set to 1 after A/D conversion ends and the ADIE bit is set to 1, an ADI interrupt request is enabled.
Page 766 Section 22 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 Quantization error H'002 H'001 H'000 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 22.3 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error...
Page 767: Usage Notes
Section 22 A/D Converter 22.7 Usage Notes 22.7.1 Module Stop Mode Setting The A/D converter operation can be enabled or disabled using the module stop control register. With the initial setting, the A/D converter is stopped. Register access is enabled by canceling module stop mode.
Page 768: Influences On Absolute Accuracy
Section 22 A/D Converter 22.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss.
Page 769: Notes On Noise Countermeasures
Section 22 A/D Converter 22.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage of the analog input pins (AN0 to AN15) and analog reference voltage pin (AVref) due to an abnormal voltage such as an excessive surge should be connected between AVcc and AVss, as shown in figure 22.6.
Page 770: Module Stop Mode Setting
Section 22 A/D Converter Table 22.7 Analog Pin Specifications Item Min. Max. Unit  Analog input capacitance  Permissible signal-source kΩ impedance 10 kΩ AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 22.7 Analog Input Pin Equivalent Circuit 22.7.7 Module Stop Mode Setting When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are...
Page 771: Note On Activation Of The A/D Converter By An External Trigger
Section 22 A/D Converter 22.7.8 Note on Activation of the A/D Converter by an External Trigger When starting of the A/D converter by an external trigger* is in use, any of the following actions (1. to 3.) may lead to a situation where stopping of the A/D converter is not possible. Note: * External trigger: Conversion-start trigger from the peripheral modules (TMU and TPU) 1.
Page 772 Section 22 A/D Converter Extaernal trigger shut off? ADCR.TRGS1 = 0 ADCR.TRGS0 = 0 (to invalidate the external trigger)* ADCSR.ADST = 0 Change the scan mode change the extaernal trigger setting* Note * Overwrite the TRGS1 and TRGS0 bits settings at the same time (in a byte unit). Figure 22.8 Procedure for Changing Modes when Starting of the A/D Converter by an External Trigger has been Selected Rev.
Page 773: Section 23 Ram
Section 23 RAM Section 23 RAM This LSI has 8 Kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 774 Section 23 RAM Rev. 1.00 Apr. 28, 2008 Page 748 of 994 REJ09B0452-0100...
Page 775: Section 24 Flash Memory
Section 24 Flash Memory Section 24 Flash Memory The flash memory has the following features. Figure 24.1 is a block diagram of the flash memory. 24.1 Features • Size Product Classification ROM Size ROM Address H8S/2117R R4F2117R 160 kbytes H'000000 to H'027FFF (mode 2) •...
Page 776: Mode Transition Diagram
Section 24 Flash Memory Internal address bus Internal data bus (16 bits) FCCS FPCS Memory MAT unit FECS Control unit FKEY User MAT: 160 kbytes User boot MAT: 8 kbytes FTDAR FMATS Flash memory Operating Mode pins mode [Legend] FCCS: Flash code control/status register FPCS: Flash program code select register...
Page 777 Section 24 Flash Memory RES = 0 Programmer mode Programmer mode setting Reset state End of programming/ erasure User User program Boot mode User mode boot mode Start of mode programming/ erasure On-board programming mode Figure 24.2 Mode Transition of Flash Memory Table 24.1 Differences between Boot Mode, User Program Mode, and Programmer Mode Programmer Item...
Page 778: Flash Memory Mat Configuration
Section 24 Flash Memory 24.3 Flash Memory MAT Configuration This LSI's flash memory is configured by the 160-Kbyte user MAT and 8-Kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when program execution or data access is performed between two MATs, the MAT must be switched by using FMATS.
Page 779: Block Structure
Section 24 Flash Memory 24.4 Block Structure Figure 24.4 shows the 160-kbyte block structure. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames indicates the addresses. The 160-kbyte user MAT is divided into one 64-kbyte block, two 32-kbyte blocks, and eight 4-kbyte blocks.
Page 780: Programming/Erasing Interface
Section 24 Flash Memory 24.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters.
Page 781 Section 24 Flash Memory Selection of On-Chip Program to be Downloaded This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR).
Page 782: Input/Output Pins
Section 24 Flash Memory When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively.
Page 783: Register Descriptions
Section 24 Flash Memory 24.7 Register Descriptions The flash memory has the following registers and parameters. Table 24.3 Register Configuration Initial Data Bus Register Name Abbreviation R/W Value Address Width Flash code control status register FCCS R/W* H'80 H'FEA8 Flash program code select register FPCS H'00 H'FEA9...
Page 784 Section 24 Flash Memory There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT. The correspondence between operating modes and registers/parameters for use is shown in table 24.5. Table 24.5 Registers/Parameters and Target Modes Initiali- Program-...
Page 785: Programming/Erasing Interface Registers
Section 24 Flash Memory 24.7.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM.
Page 786 Section 24 Flash Memory Initial Bit Name Value Description  3 to 1 All 0 Reserved These are read-only bits and cannot be modified. (R)/W* Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR.
Page 787 Section 24 Flash Memory Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Initial Bit Name Value Description  7 to 1 All 0 Reserved These are read-only bits and cannot be modified. PPVS Program Pulse Verify Selects the programming program to be downloaded.
Page 788 Section 24 Flash Memory Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Initial Bit Name Value Description Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled.
Page 789 Section 24 Flash Memory Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Initial Bit Name Value Description 0/1* MAT Select The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected 0/1* when H'AA is written.
Page 790 Section 24 Flash Memory Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Initial Bit Name Value Description...
Page 791: Programming/Erasing Interface Parameters
Section 24 Flash Memory 24.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area.
Page 792 Section 24 Flash Memory (b) Initialization before Programming/Erasing The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set.
Page 793 Section 24 Flash Memory Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in On- Chip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result.
Page 794 Section 24 Flash Memory Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. Initialization before programming/erasing FPFR indicates the return value of the initialization result.
Page 795 Section 24 Flash Memory (b) Programming FPFR indicates the return value of the programming result. Initial Bit Name Value Description    Unused Returns 0.  Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1.
Page 796 Section 24 Flash Memory Initial Bit Name Value Description  Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination...
Page 797 Section 24 Flash Memory Erasure FPFR indicates the return value of the erasure result. Initial Bit Name Value Description    Unused Returns 0.  Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1.
Page 798 Section 24 Flash Memory Initial Bit Name Value Description  Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal ...
Page 799 Section 24 Flash Memory Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 20 MHz. Initial Bit Name Value Description 31 to 16 ...
Page 800 Section 24 Flash Memory Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs.
Page 801 Section 24 Flash Memory Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values range from 0 to 10 (H'00000000 to H'0000000A). A value of 0 corresponds to block EB0 and a value of 10 corresponds to block EB10.
Page 802: On-Board Programming Mode
Section 24 Flash Memory 24.8 On-Board Programming Mode When the mode pins (MD1 and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased.
Page 803 Section 24 Flash Memory Serial Interface Setting by Host The SCI_1 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_1 to match that of the host.
Page 804 Section 24 Flash Memory State Transition Diagram The state transition after boot mode is initiated is shown in figure 24.8. (Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Boot mode initiation Bit rate adjustment (reset by boot mode) Inquiry command reception Processing of Wait for inquiry...
Page 805 Section 24 Flash Memory 1. After boot mode is initiated, the bit rate of the SCI_1 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3.
Page 806: User Program Mode
Section 24 Flash Memory 24.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The programming/erasing flow is shown in figure 24.10. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state must not be made during programming/erasing.
Page 807 Section 24 Flash Memory On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the on- chip program and procedure program do not overlap.
Page 808 Section 24 Flash Memory Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 24.12. Start programming procedure program Select on-chip program Disable interrupts and bus to be downloaded and master operation specify download other than CPU...
Page 809 Section 24 Flash Memory The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the on- chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data.
Page 810 Section 24 Flash Memory  To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed.  Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1.
Page 811 Section 24 Flash Memory 7. The return value in the initialization program, the FPFR parameter is determined. 8. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing.
Page 812 Section 24 Flash Memory 12. The return value in the programming program, the FPFR parameter is determined. 13. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14.
Page 813 Section 24 Flash Memory Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 24.13. Start erasing procedure program Select on-chip program to be downloaded and Disable interrupts and specify download bus master operation destination by FTDAR...
Page 814 Section 24 Flash Memory One erasure processing erases one block. For details on block divisions, refer to figure 24.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected.
Page 815: User Boot Mode
Section 24 Flash Memory 24.8.3 User Boot Mode This LSI has user boot mode that is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI.
Page 816 Section 24 Flash Memory Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT switchover Set FKEY to H'A5 Set FKEY to H'A5 Set SCO to 1 and execute download Set parameters to...
Page 817 Section 24 Flash Memory MAT switching is enabled by writing a specific value to FMATS. Note, however, that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined.
Page 818 Section 24 Flash Memory Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT switchover Set FKEY to H'A5 Set FKEY to H'A5 Set SCO to 1 and execute download Set FEBS parameter...
Page 819: Storable Areas For On-Chip Program And Program Data
Section 24 Flash Memory Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data. 24.8.4 Storable Areas for On-Chip Program and Program Data In the descriptions in this manual, the on-chip programs and program data storage areas are...
Page 820 Section 24 Flash Memory In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 24.9 to 24.13. Table 24.9 Executable Memory MAT Operating Mode Processing Contents...
Page 821 Section 24 Flash Memory Table 24.11 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-Chip RAM User MAT User MAT Storage MAT Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 822 Section 24 Flash Memory Table 24.12 Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT Embedded User Boot User Boot Program Item On-chip RAM User MAT Storage MAT Ο ×*    Storage area for program data Ο...
Page 823 Section 24 Flash Memory Table 24.13 Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT Embedded User Boot User Boot Program Item On-chip RAM User MAT Storage MAT Ο Ο Ο Selecting on-chip program to be downloaded Ο...
Page 824: Protection
Section 24 Flash Memory 24.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection.
Page 825: Software Protection
Section 24 Flash Memory 24.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program and using the key code. Table 24.15 Software Protection Function to be Protected Programming/ Item Description Download Erasing Protection The programming/erasing protection state is...
Page 826 Section 24 Flash Memory Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100µs has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released.
Page 827: Switching Between User Mat And User Boot Mat
Section 24 Flash Memory 24.10 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing.
Page 828: Programmer Mode
Section 24 Flash Memory 24.11 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 24.16 can be used to write programs to the on-chip ROM without any limitation.
Page 829 Section 24 Flash Memory 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host.
Page 830 Section 24 Flash Memory Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state.
Page 831 Section 24 Flash Memory 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of four bytes of data. One-byte command Command or response or one-byte response...
Page 832 Section 24 Flash Memory Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command.
Page 833 Section 24 Flash Memory The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40).
Page 834 Section 24 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code...
Page 835 Section 24 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock- mode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size...
Page 836 Section 24 Flash Memory Division Ratio Inquiry The boot program will return the supported division ratios in response to the inquiry. Command H'22 • Command, H'22, (one byte): Inquiry regarding division ratio Response H'32 Size Number of types … Number of division Division ratios ratio...
Page 837 Section 24 Flash Memory Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 • Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Minimum value of...
Page 838 Section 24 Flash Memory User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 • Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Start address area Last address area …...
Page 839 Section 24 Flash Memory (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 • Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Start address area Last address area …...
Page 840 Section 24 Flash Memory • Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. • SUM (one byte): Checksum Programming Unit Inquiry The boot program will return the programming unit used to program data.
Page 841 Section 24 Flash Memory • Number of division ratios (one byte): The number of division ratios to which the device can be set. There are usually two division ratios, which are the main and peripheral module operating frequencies. • Division ratio 1 (one byte): The value of division ratios for the main operating frequency Division ratio: The inverse of the division ratio, as a negative number (e.g.
Page 842 Section 24 Flash Memory Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated.
Page 843 Section 24 Flash Memory The sequence of new bit-rate selection is shown in figure 24.21. Boot program Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 24.21 New Bit-Rate Selection Sequence...
Page 844 Section 24 Flash Memory Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx...
Page 845 Section 24 Flash Memory Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 24.18 lists the programming/erasing commands.
Page 846 Section 24 Flash Memory 1. Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command. After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command.
Page 847 Section 24 Flash Memory 2. Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased.
Page 848 Section 24 Flash Memory 3. Programming/Erasing State Information User Boot MAT Programming Selection The boot program will transfer a program for user boot MAT programming selection. The data is programmed to the user boot MATs by the transferred program for programming. Command H'42 •...
Page 849 Section 24 Flash Memory 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user MATs in response to 128-byte programming. Command H'50 Address … Data … • Command, H'50, (one byte): 128-byte programming •...
Page 850 Section 24 Flash Memory Command H'50 Address • Command, H'50, (one byte): 128-byte programming • Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Page 851 Section 24 Flash Memory Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number • Command, H'58, (one byte): Erasure • Size (one byte): The number of bytes that represents the erase block number This is fixed to 1.
Page 852 Section 24 Flash Memory Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address Read size • Command: H'52 (1 byte): Memory read • Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) •...
Page 853 Section 24 Flash Memory User Boot MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user boot MAT. Command H'4A • Command, H'4A, (one byte): Sum check for user boot MAT Response H'5A Size...
Page 854 Section 24 Flash Memory User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C • Command, H'4C, (one byte): Blank check for user boot MATs Response H'06 •...
Page 855 Section 24 Flash Memory (k) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F • Command, H'4F, (one byte): Inquiry regarding boot program's state Response H'5F...
Page 856 Section 24 Flash Memory Table 24.20 Error Codes Code Description H'00 No error H'11 Sum check error H'12 Program size error H'21 Device code mismatch error H'22 Clock mode mismatch error H'24 Bit rate selection error H'25 Input frequency error H'26 Division ratio error H'27...
Page 857: Usage Notes
Section 24 Flash Memory 24.13 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating.
Page 858 Section 24 Flash Memory 12. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and version of program. 13.
Page 859: Section 25 Clock Pulse Generator
Section 25 Clock Pulse Generator Section 25 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, subclock input circuit, and subclock waveform forming circuit.
Page 860: Oscillator
Section 25 Clock Pulse Generator 25.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 25.1.1 Connecting Crystal Resonator Figure 25.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance R , given in table 25.1 should be used.
Page 861: External Clock Input Method
Section 25 Clock Pulse Generator Table 25.2 Crystal Resonator Parameters Frequency (MHz) (max) (Ω) (max) (pF) 25.1.2 External Clock Input Method Figure 25.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode or watch mode.
Page 862 Section 25 Clock Pulse Generator Table 25.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item Symbol Min. Max. Unit Test Conditions  External clock input pulse Figure 25.5 width low level  External clock input pulse width high level ...
Page 863 Section 25 Clock Pulse Generator Table 25.4 External Clock Output Stabilization Delay Time Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Item Symbol Min. Max. Unit Remarks ...
Page 864: Duty Correction Circuit
Section 25 Clock Pulse Generator 25.2 Duty Correction Circuit The duty correction circuit generates the system clock (φ) by correcting the duty of the clock output from the oscillator. 25.3 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin.
Page 865: Subclock Waveform Forming Circuit
Section 25 Clock Pulse Generator EXCLH EXCLL × 0.5 EXCL EXCLr EXCLf Figure 25.8 Subclock Input Timing 25.4 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform forming circuit samples the subclock using a divided φ clock. The sampling frequency is set by the NESEL bit in LPWRCR.
Page 866: Usage Notes
Section 25 Clock Pulse Generator 25.6 Usage Notes 25.6.1 Notes on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user.
Page 867: Section 26 Power-Down Modes
Section 26 Power-Down Modes Section 26 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has four power-down operating modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules.
Page 868: Standby Control Register (Sbycr)
Section 26 Power-Down Modes 26.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Initial Bit Name Value Description SSBY Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high- speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode or watch mode...
Page 869 Section 26 Power-Down Modes Initial Bit Name Value Description SCK2 System Clock Select 2 to 0 SCK1 These bits select a clock for the bus master in high- speed mode or medium-speed mode. SCK0 When making a transition to watch mode, these bits must be cleared to B'000.
Page 870: Low-Power Control Register (Lpwrcr)
Section 26 Power-Down Modes 26.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Initial Bit Name Value Description DTON Direct Transfer On Flag The initial value should not be changed. LSON Low-Speed On Flag The initial value should not be changed. NESEL Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (φSUB)
Page 871: Module Stop Control Registers H, L, A, And B
Section 26 Power-Down Modes 26.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. •...
Page 872 Section 26 Power-Down Modes • MSTPCRA Bit Name Initial Value R/W Corresponding Module MSTPA7 1 Reserved The initial value should not be changed. MSTPA6 1 Duty period measurement timer_0 (TDP_0) MSTPA5 1 Duty period measurement timer_1 (TDP_1) MSTPA4 1 Duty period measurement timer_2 (TDP_2) MSTPA3 1 CIR interface (CIR) MSTPA2 1...
Page 873 Section 26 Power-Down Modes The PWMX sets operation or stop by a combination of bits as follows: MSTPCRH: MSTPCRA: MSTP11 MSTPA1 Function 14-bit PWM timer (PWMX) operates. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. Note: The MSTP11 bit in MSTPCRH is a module stop bit of the PWMX.
Page 874: Mode Transitions And Lsi States
Section 26 Power-Down Modes 26.2 Mode Transitions and LSI States Figure 26.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The RES input causes a mode transition from any state to the reset state.
Page 875 Section 26 Power-Down Modes Table 26.3 LSI Internal States in Each Operating Mode Software Function High Speed Medium Speed Sleep Module Stop Watch Standby System clock pulse Functioning Functioning Functioning Functioning Stopped Stopped generator Subclock input Functioning Functioning Functioning Functioning Functioning Stopped Instruction...
Page 876: Medium-Speed Mode
Section 26 Power-Down Modes 26.3 Medium-Speed Mode The operating mode changes to medium-speed mode as soon as the current bus cycle ends by the settings of the SCK2 to SCK0 bits in SBYCR. The operating clock can be selected from φ/2, φ/4, φ/8, φ/16, or φ/32.
Page 877: Sleep Mode
Section 26 Power-Down Modes 26.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the on-chip peripheral modules do not.
Page 878 Section 26 Power-Down Modes When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling.
Page 879: Watch Mode
Section 26 Power-Down Modes 26.6 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
Page 880: Module Stop Mode
Section 26 Power-Down Modes 26.7 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle.
Page 881: Section 27 List Of Registers
Section 27 List of Registers Section 27 List of Registers The list of registers gives information on the on-chip register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module.
Page 882: Register Addresses (Address Order)
Section 27 List of Registers 27.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits. The number of access states indicates the number of states based on the specified reference clock. Number Data Access Register Name Abbreviation of bits Address...
Page 883 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port 5 data direction register P5DDR H'F920 PORT (PORTS = 1) Port 6 data direction register P6DDR H'F921 PORT (PORTS = 1) Port 5 data register P5DR H'F922 PORT...
Page 884 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port B data direction register PBDDR H'F951 PORT (PORTS = 1) Port A output data register PAODR H'F952 PORT (PORTS = 1) Port B output data register PBODR H'F953 PORT...
Page 885 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port F data direction register PFDDR H'F971 PORT (PORTS = 1) Port F output data register PFODR H'F973 PORT (PORTS = 1) Port E input data register PEPIN H'F974 (Read) PORT...
Page 886 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port I data direction register PIDDR H'F990 PORT Port J data direction register PJDDR H'F991 PORT Port I output data register PIODR H'F992 PORT Port J output data register PJODR...
Page 887 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States TDP timer counter_0 TDPCNT_0 H'FB40 TDP_0 TDP pulse width upper limit TDPWDMX_0 H'FB42 TDP_0 register_0 TDP pulse width lower limit TDPWDMN_0 16 H'FB44 TDP_0 register_0 TDP cycle upper limit register_0...
Page 888 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States TDP input capture register_2 TDPICR_2 H'FB88 TDP_2 TDP input capture buffer register_2 TDPICRF_2 H'FB8A TDP_2 TDP status register_2 TDPCSR_2 H'FB8C TDP_2 TDP control register 1_2 TDPCR1_2 H'FB8D TDP_2...
Page 889 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States TCM input capture register_3 TCMICR_3 H'FBF4 TCM_3 TCM input capture buffer register_3 TCMICRF_3 H'FBF6 TCM_3 TCM status register_3 TCMCSR_3 H'FBF8 TCM_3 TCM control register_3 TCMCR_3 H'FBF9 TCM_3...
Page 890 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Modem status register FMSR H'FC26 SCIF Scratch pad register FSCR H'FC27 SCIF SCIF control register SCIFCR H'FC28 SCIF FSIHBARH H'FC50 FSI access host base address register H FSIHBARL H'FC51...
Page 891 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States FSI write data register HH FSIWDRHH H'FC6A FSI write data register HL FSIWDRHL H'FC6B FSI write data register LH FSIWDRLH H'FC6C FSI write data register LL FSIWDRLL H'FC6D FSILPC command status register 2...
Page 892 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States PWM prescaler register 5_A PWMPRE5_A H'FD0B PWMU_A 8 PWM control register A_A PWMCONA_A 8 H'FD0C PWMU_A 8 PWM control register B_A PWMCONB_A 8 H'FD0D PWMU_A 8 PWM control register C_A...
Page 893 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States SCIF address register H SCIFADRH H'FDC4 SCIF address register L SCIFADRL H'FDC5 LPC channel 4 address register H LADR4H H'FDD4 LPC channel 4 address register L LADR4L H'FDD5 Input data register 4...
Page 894 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port control register 1 PTCNT1 H'FE11 PORT Port control register 2 PTCNT2 H'FE12 PORT Port 9 pull-up MOS control register P9PCR H'FE14 PORT (PORTS = 0) Port G Nch-OD control register PGNOCR...
Page 895 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States LPC channel 3 address register L LADR3L H'FE35 SERIRQ control register 0 SIRQCR0 H'FE36 SERIRQ control register 1 SIRQCR1 H'FE37 Input data register 1 IDR1 H'FE38 Output data register 1...
Page 896 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port C input data register PCPIN H'FE4E (Read) PORT (PORTS = 0) Port C data direction register PCDDR H'FE4E (Write) PORT (PORTS = 0) Port D input data register PDPIN H'FE4F (Read)
Page 897 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Keyboard matrix interrupt register A KMIMRA H'FE83 (RELOCATE = 1) Wake-up sense control register WUESCR H'FE84 Wake-up input interrupt status WUESR H'FE85 register Wake-up enable register H'FE86 Interrupt control register D...
Page 898 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Flash transfer destination address FTDAR H'FEAE register Timer start register TSTR H'FEB0 common Timer synchro register TSYR H'FEB1 common Keyboard control register 1_0 KBCR1_0 H'FEC0 PS2_0...
Page 899 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Keyboard control register 1_3 KBCR1_3 H'FED2 PS2_3 Keyboard data buffer transmit data KBTR_3 H'FED3 PS2_3 register_3 C bus control extended register_0 ICXR_0 H'FED4 IIC_0 C bus control extended register_1 ICXR_1...
Page 900 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Transmit data register_2 TDR_2 H'FFA3 SCI_2 Serial status register_2 SSR_2 H'FFA4 SCI_2 Receive data register_2 RDR_2 H'FFA5 SCI_2 Smart card mode register_2 SCMR_2 H'FFA6 SCI_2 PWMX(D/A) counter H...
Page 901 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port 3 data direction register P3DDR H'FFB4 PORT (PORTS = 0) Port 4 data direction register P4DDR H'FFB5 PORT (PORTS = 0) Port 3 data register P3DR H'FFB6 PORT...
Page 902 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Timer control register_0 TCR_0 H'FFC8 TMR_0 Timer control register_1 TCR_1 H'FFC9 TMR_1 Timer control/status register_0 TCSR_0 H'FFCA TMR_0 Timer control/status register_1 TCSR_1 H'FFCB TMR_1 Time constant register A_0 TCORA_0...
Page 903 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Input capture register R TICRR H'FFF2 TMR_X Time constant register A_Y TCORA_Y H'FFF2 TMR_Y (RELOCATE = 0) Input capture register F TICRF H'FFF3 TMR_X Time constant register B_Y TCORB_Y...
Page 904: Register Bits
Section 27 List of Registers 27.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 905 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDPCNT_0 TDP_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6...
Page 906 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDP_1 TDPCSR_1 ICPF CKSEG TWDMXOVF TWDMNUDF TPDMXOVF TPDMNUDF TDPCR1_1 POCTL CPSPE IEDG TDPMDS CKS2 CKS1 CKS0 TDPIER_1 OVIE TWDMXIE TWDMNIE TPDMXIE...
Page 907 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TCM_0 TCMCSR_0 MAXOVF CKSEG ICPF MINUDF MCICTL TCMCR_0 POCTL CPSPE IEDG TCMMDS CKS2 CKS1 CKS0 ...
Page 908 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCMCNT_3 TCM_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6...
Page 909 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SCIF FRBR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FTHR bit 7...
Page 910 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FSIGPRC bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FSIGPRD bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FSIGPRE...
Page 911 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PWMREG0_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWMU_A PWMPRE0_A bit 7 bit 6...
Page 912 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TPU_1 TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0     TMDR_1 TIOR_1 IOB3 IOB2 IOB1...
Page 913 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT PGNCMC PG7NCMC PG6NCMC PG5NCMC PG4NCMC PG3NCMC PG2NCMC PG1NCMC PG0NCMC      PGNCCS PGNCCK2 PGNCCK1 PGNCCK0 ...
Page 914 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ODR3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STR3* IBF3B OBF3B...
Page 915 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT PDPIN PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR...
Page 916 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR PORT...
Page 917 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module      TSTR CST2 CST1 CST0 common      TSYR SYNC2 SYNC1 SYNC0...
Page 918 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PS2_2 KBCRH_2 KBIOE KCLKI KBFSEL KBIE  KBCRL_2 KCLKO RXCR3 RXCR2 RXCR1 RXCR0 KBBR_2   ...
Page 919 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SCI_1 SSR_1* TDRE RDRF ORER TEND MPBT (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) RDR_1 bit 7 bit 6 bit 5...
Page 920 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PBPIN PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN...
Page 921 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PS2_3 KBCRH_3 KBIOE KCLKI KBFSEL KBIE  KBCRL_3 KCLKO RXCR3 RXCR2 RXCR1 RXCR0 KBBR_3   ...
Page 922: Register States In Each Operating Mode
Section 27 List of Registers 27.3 Register States in Each Operating Mode High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      PIDDR Initialized PORT      PJDDR Initialized ...
Page 923 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      TDPCNT_0 Initialized TDP_0      TDPPDMX_0 Initialized      TDPPDMN_0 Initialized ...
Page 924 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      TDPCR1_2 Initialized TDP_2      TDPIER_2 Initialized      TDPCR2_2 Initialized ...
Page 925 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      TCMCNT_3 Initialized TCM_3      TCMMLCM_3 Initialized      TCMICR_3 Initialized ...
Page 926 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      FSIHBARH Initialized      FSIHBARL Initialized      FSISR Initialized  ...
Page 927 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      FSIWDRLH Initialized      FSIWDRLL Initialized      FSICR1 Initialized  ...
Page 928 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module   PWMCONA_A Initialized Initialized Initialized Initialized PWMU_A   PWMCONB_A Initialized Initialized Initialized Initialized   PWMCONC_A Initialized Initialized Initialized Initialized ...
Page 929 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      LADR1H Initialized      LADR1L Initialized      LADR2H Initialized  ...
Page 930 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      P9PCR Initialized PORT      PGNOCR Initialized      PFNOCR Initialized ...
Page 931 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      IDR1 Initialized      ODR1 Initialized      STR1 Initialized  ...
Page 932 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      TGRA_0 Initialized TPU_0      TGRB_0 Initialized      TGRC_0 Initialized ...
Page 933 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module   DACR Initialized Initialized Initialized Initialized PWMX   DADRA Initialized Initialized Initialized Initialized   DADRB Initialized Initialized Initialized Initialized ...
Page 934 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      KBCR1_3 Initialized PS2_3      KBTR_3 Initialized      ICXR_0 Initialized IIC_0 ...
Page 935 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      ISCR16L Initialized      ISSR16 Initialized      ISSR Initialized  ...
Page 936 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      P1DDR Initialized PORT      P2DDR Initialized      P1DR Initialized ...
Page 937 Section 27 List of Registers High- Register Speed/Medium Module Software Abbreviation Reset speed Watch Sleep Stop Standby Module      TCORA_0 Initialized TMR_0, TMR_1      TCORA_1 Initialized      TCORB_0 Initialized ...
Page 938: Register Selection Condition
Section 27 List of Registers 27.4 Register Selection Condition Register Lower Address Abbreviation Register Selection Condition Module H'F900 P1DDR PORTS = 1 PORT H'F901 P2DDR H'F902 P1DR H'F903 P2DR H'F904 P1PIN (Read) H'F905 P2PIN (Read) H'F907 P2PCR H'F910 P3DDR H'F911 P4DDR H'F912 P3DR...
Page 939 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'F944 P9PIN (Read) PORTS = 1 PORT H'F946 P9PCR H'F950 PADDR H'F951 PBDDR H'F952 PAODR H'F953 PBODR H'F954 PAPIN (Read) H'F955 PBPIN (Read) H'F957 PBPCR H'F960 PCDDR H'F961 PDDDR H'F962...
Page 940 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'F983 PHODR PORTS = 1 PORT H'F984 PGPIN (Read) H'F985 PHPIN (Read) H'F987 PHPCR H'F988 PGNOCR H'F989 PHNOCR H'F98A PGNCE H'F98C PGNCMC H'F98E PGNCCS H'F990 PIDDR No condition H'F991 PJDDR H'F992...
Page 941 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FA4F DT1MAX MSTPA3 = 0 H'FA50 RMIN H'FA51 RMAX H'FB40 TDPCNT_0 MSTPA6 = 0 TDP_0 H'FB42 TDPWDMX_0 H'FB44 TDPWDMN_0 H'FB46 TDPPDMX_0 H'FB48 TDPICR_0 H'FB4A TDPICRF_0 H'FB4C TDPCSR_0 H'FB4D TDPCR1_0 H'FB4E...
Page 942 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FB8A TDPICRF_1 H'FB8C TDPCSR_1 H'FB8D TDPCR1_1 H'FB8E TDPIER_1 H'FB8F TDPCR2_1 H'FB90 TDPPDMN_1 H'FBC0 TCMCNT_0 MSTPB1 = 0 TCM_0 H'FBC2 TCMMLCM_0 H'FBC4 TCMICR_0 H'FBC6 TCMICRF_0 H'FBC8 TCMCSR_0 H'FBC9 TCMCR_0 H'FBCA TCMIER_0...
Page 943 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FBF0 TCMCNT_3 MSTPB2 = 0 TCM_3 H'FBF2 TCMMLCM_3 H'FBF4 TCMICR_3 H'FBF6 TCMICRF_3 H'FBF8 TCMCSR_3 H'FBF9 TCMCR_3 H'FBFA TCMIER_3 H'FBFC TCMMINCM_3 H'FC00 ADDRA MSTP9 = 0 A/D converter H'FC02 ADDRB H'FC04...
Page 944 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FC50 FSIHBARH MSTP0 = 0 MSTPA2 = 0 H'FC51 FSIHBARL H'FC52 FSISR H'FC53 CMDHBARH H'FC54 CMDHBARL H'FC55 FSICMDR H'FC56 FSILSTR1 H'FC57 FSIGPR1 H'FC58 FSIGPR2 H'FC59 FSIGPR3 H'FC5A FSIGPR4 H'FC5B FSIGPR5...
Page 945 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FC90 FSICR1 MSTP0 = 0 MSTPA2 = 0 H'FC91 FSICR2 H'FC92 FSIBNR H'FC93 FSIINS H'FC94 FSIRDINS H'FC95 FSIPPINS H'FC96 FSISTR H'FC98 FSITDR0 H'FC99 FSITDR1 H'FC9A FSITDR2 H'FC9B FSITDR3 H'FC9C FSITDR4...
Page 946 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FD10 PWMREG0_B MSTPB0 = 0 PWMU_B H'FD11 PWMPRE0_B H'FD12 PWMREG1_B H'FD13 PWMPRE1_B H'FD14 PWMREG2_B H'FD15 PWMPRE2_B H'FD16 PWMREG3_B H'FD17 PWMPRE3_B H'FD18 PWMREG4_B H'FD19 PWMPRE4_B H'FD1A PWMREG5_B H'FD1B PWMPRE5_B H'FD1C PWMCONA_B...
Page 947 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FDC0 LADR1H MSTP0 = 0 H'FDC1 LADR1L H'FDC2 LADR2H H'FDC3 LADR2L H'FDC4 SCIFADRH H'FDC5 SCIFADRL H'FDD4 LADR4H H'FDD5 LADR4L H'FDD6 IDR4 H'FDD7 ODR4 H'FDD8 STR4 H'FDD9 HICR4 H'FDDA SIRQCR2 H'FDDB...
Page 948 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FE10 PTCNT0 No condition PORT H'FE11 PTCNT1 H'FE12 PTCNT2 H'FE14 P9PCR PORTS = 0 H'FE16 PGNOCR H'FE19 PFNOCR H'FE1C PCNOCR H'FE1D PDNOCR H'FE20 TWR0MW MSTP0 = 0 TWR0SW H'FE21 TWR1...
Page 949 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FE32 STR3 MSTP0 = 0 H'FE33 HICR5 H'FE34 LADR3H H'FE35 LADR3L H'FE36 SIRQCR0 H'FE37 SIRQCR1 H'FE38 IDR1 H'FE39 ODR1 H'FE3A STR1 H'FE3B SIRQCR4 H'FE3C IDR2 H'FE3D ODR2 H'FE3E STR2 H'FE3F...
Page 950 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FE50 TCR_0 MSTP1 = 0 TPU_0 H'FE51 TMDR_0 H'FE52 TIORH_0 H'FE53 TIORL_0 H'FE54 TIER_0 H'FE55 TSR_0 H'FE56 TCNT_0 H'FE58 TGRA_0 H'FE5A TGRB_0 H'FE5C TGRC_0 H'FE5E TGRD_0 H'FE70 TCR_2 TPU_2 H'FE71...
Page 951 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FE88 ICCR_2 MSTPB4 = 0 IIC_2 H'FE89 ICSR_2 H'FE8A ICRES_2 H'FE8C ICXR_2 H'FE8E ICDR_2 ICE in ICCR_2 = 1 H'FE8E SARX_2 ICE in ICCR_2 = 0 H'FE8F ICMR_2 ICE in ICCR_2 = 1 H'FE8F...
Page 952 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FEB0 TSTR MSTP1 = 0 TPU common H'FEB1 TSYR H'FEC0 KBCR1_0 MSTP2 = 0 H'FEC1 KBTR_0 H'FEC2 KBCR1_1 H'FEC3 KBTR_1 H'FEC4 KBCR1_2 H'FEC5 KBTR_2 H'FEC6 TCRXY MSTP8 = 0 TMR_XY H'FEC8 TCR_Y...
Page 953 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FED2 KBCR1_3 MSTPB5 PS2_3 H'FED3 KBTR_3 H'FED4 ICXR_0 MSTP4 = 0 IIC_0 H'FED5 ICXR_1 MSTP3 = 0 IIC_1 H'FED8 KBCRH_0 MSTP2 = 0 H'FED9 KBCRL_0 H'FEDA KBBR_0 H'FEDB KBCR2_0 H'FEDC...
Page 954 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FEFC ISSR16 No condition H'FEFD ISSR H'FF82 PCSR FLSHE in STCR = 0 PWMX (RELOCATE = 0) PCSR No condition (RELOCATE = 1) H'FF84 SBYCR FLSHE in STCR = 0 SYSTEM (RELOCATE = 0) SBYCR...
Page 955 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FF8A SCR_1 MSTP6 = 0 SCI_1 H'FF8B TDR_1 H'FF8C SSR_1 H'FF8D RDR_1 H'FF8E SCMR_1 MSTP6 = 0 (RELOCATE = 1) SCMR_1 MSTP6 = 0, IICE in STCR = 0 (RELOCATE = 0) ICDR_1 MSTP3 = 0...
Page 956 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FFA5 RDR_2 MSTP5 = 0 SCI_2 H'FFA6 SCMR_2 H'FFA7 DADRBL MSTP11 = 0 REGS in DACNT/ PWMX (RELOCATE = 0) MSTPA1 = 0 DADRB = 0 IICE in STCR = 1 DACNTL REGS in DACNT/ (RELOCATE = 0)
Page 957 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FFBE P7PIN (Read) PORTS = 0 PORT PBDDR (Write) H'FFBF P8DR H'FFC0 P9DDR H'FFC1 P9DR H'FFC2 No condition H'FFC3 STCR No condition SYSTEM H'FFC4 SYSCR H'FFC5 MDCR H'FFC6 No condition H'FFC7...
Page 958 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FFE0 KBCRH_3 MSTPB5 = 0 PS2_3 H'FFE1 KBCRL_3 H'FFE2 KBBR_3 H'FFE3 KBCR2_3 H'FFEA TCSR_1 No condition WDT_1 TCNT_1 (Write) H'FFEB TCNT_1 (Read) H'FFF0 TCR_X MSTP8 = 0 TMR_X (RELOCATE = 1) TCR_X...
Page 959 Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FFF3 KMIMRA MSTP2 = 0, KINWUE in SYSCR = 1 (RELOCATE = 0) TICRF MSTP8 = 0 TMR_X (RELOCATE = 1) TICRF MSTP8 = 0 TMRX/Y (RELOCATE = 0) KINWUE in SYSCR = 0 in TCONRS = 0 TCORB_Y...
Page 960: Register Addresses (Classification By Type Of Module)
Section 27 List of Registers 27.5 Register Addresses (Classification by Type of Module) Register Number of Data Bus Access Module Abbreviation Bits Address Width States WUEMR H'FE45 KMIMR H'FE81 (RELOCATE = 1) KMIMRA H'FE83 (RELOCATE = 1) WUESCR H'FE84 WUESR H'FE85 H'FE86 ICRD...
Page 961 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States H'FFC6 WSCR H'FFC7 PORT P1DDR H'F900 (PORTS = 1) PORT P2DDR H'F901 (PORTS = 1) PORT P1DR H'F902 (PORTS = 1) PORT P2DR H'F903 (PORTS = 1) PORT...
Page 962 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT P5DR H'F922 (PORTS = 1) PORT P6DR H'F923 (PORTS = 1) PORT P5PIN H'F924 (Read) (PORTS = 1) PORT P6PIN H'F925 (Read) (PORTS = 1) PORT P6NCE...
Page 963 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT PBODR H'F953 (PORTS = 1) PORT PAPIN H'F954 (Read) (PORTS = 1) PORT PBPIN H'F955 (Read) (PORTS = 1) PORT PBPCR H'F957 (PORTS = 1) PORT PCDDR...
Page 964 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT PFODR H'F973 (PORTS = 1) PORT PEPIN H'F974 (Read) (PORTS = 1) PORT PFPIN H'F975 (Read) (PORTS = 1) PORT PFPCR H'F977 (PORTS = 1) PORT PFNOCR...
Page 965 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT PIODR H'F992 PORT PJODR H'F993 PORT PIPIN H'F994 (Read) PORT PJPIN H'F995 (Read) PORT PJPCR H'F997 PORT PINOCR H'F998 PORT PJNOCR H'F999 PORT P6NCE H'FE00...
Page 966 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT PTCNT0 H'FE10 (PORTS = 0) PORT PTCNT1 H'FE11 (PORTS = 0) PORT PTCNT2 H'FE12 (PORTS = 0) PORT P9PCR H'FE14 (PORTS = 0) PORT PGNOCR H'FE16...
Page 967 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT PCODR H'FE4C (PORTS = 0) PORT PDODR H'FE4D (PORTS = 0) PORT PCPIN H'FE4E (Read) (PORTS = 0) PORT PCDDR H'FE4E (Write) (PORTS = 0) PORT PDPIN...
Page 968 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PORT P2DR H'FFB3 (PORTS = 0) PORT P3DDR H'FFB4 (PORTS = 0) PORT P4DDR H'FFB5 (PORTS = 0) PORT P3DR H'FFB6 (PORTS = 0) PORT P4DR H'FFB7...
Page 969 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States TDP_0 TDPCNT_0 H'FB40 TDP_0 TDPWDMX_0 H'FB42 TDP_0 TDPWDMN_0 H'FB44 TDP_0 TDPPDMX_0 H'FB46 TDP_0 TDPICR_0 H'FB48 TDP_0 TDPICRF_0 H'FB8A TDP_0 TDPCSR_0 H'FB8C TDP_0 TDPCR1_0 H'FB4D TDP_0 TDPIER_0...
Page 970 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States TDP_2 TDPCR2_2 H'FB8F TDP_2 TDPPDMN_2 H'FB90 TCM_0 TCMCNT_0 H'FBC0 TCM_0 TCMMLCM_0 H'FBC2 TCM_0 TCMICR_0 H'FBC4 TCM_0 TCMICRF_0 H'FBC6 TCM_0 TCMCSR_0 H'FBC8 TCM_0 TCMCR_0 H'FBC9 TCM_0 TCMIER_0...
Page 971 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States TCM_3 TCMCR_3 H'FBF9 TCM_3 TCMIER_3 H'FBFA TCM_3 TCMMINCM_3 16 H'FBFC FSIHBARH H'FC50 FSIHBARL H'FC51 FSISR H'FC52 CMDHBARH H'FC53 CMDHBARH H'FC54 FSICMDR H'FC55 FSILSTR1 H'FC56 FSIGPR1 H'FC57...
Page 972 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States FSIWDRLH H'FC6C FSIWDRLL H'FC6D FSILSTR2 H'FC6E FSICR1 H'FC90 FSICR2 H'FC91 FSIBNR H'FC92 FSINS H'FC93 FSIRDINS H'FC94 FSIPPINS H'FC95 FSISTR H'FC96 FSITDR0 H'FC98 FSITDR1 H'FC99 FSITDR2 H'FC9A...
Page 973 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States DT1MIN H'FA4E DT1MAX H'FA4F RMIN H'FA50 RMAX H'FA51 PWMU_A PWMREG0 H'FD00 PWMU_A PWMPRE0 H'FD01 PWMU_A PWMREG1 H'FD02 PWMU_A PWMPRE1 H'FD03 PWMU_A PWMREG2 H'FD04 PWMU_A PWMPRE2 H'FD05...
Page 974 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States PWMU_B PWMCONA H'FD1C PWMU_B PWMCONB H'FD1D PWMU_B PWMCONC H'FD1E PWMU_B PWMCOND H'FD1F PWMX DACR H'FEA0 (RELOCATE = 1) PWMX DADRAH H'FEA0 (RELOCATE = 1) PWMX DADRAL H'FEA1...
Page 975 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States TPU_0 TIORH_0 H'FE52 TPU_0 TIORL_0 H'FE53 TPU_0 TIER_0 H'FE54 TPU_0 TSR_0 H'FE55 TPU_0 TCNT_0 H'FE56 TPU_0 TGRA_0 H'FE58 TPU_0 TGRB_0 H'FE5A TPU_0 TGRC_0 H'FE5C TPU_0 TGRD_0...
Page 976 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States TMR_0 TCORB_0 H'FFCE TMR_0 TCNT_0 H'FFD0 TMR_1 TCR_1 H'FFC9 TMR_1 TCSR_1 H'FFCB TMR_1 TCORA_1 H'FFCD TMR_1 TCORB_1 H'FFCF TMR_1 TCNT_1 H'FFD1 TMR_X TCR_X H'FFF0 TMR_X TCSR_X...
Page 977 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States TMR_Y TCNT_Y H'FFF4 (RELOCATE = 0) TMR_XY TCRXY H'FEC6 TMR_X TCONRI H'FFFC TMR_X, TCONRS H'FFFE TMR_Y WDT_0 TCSR_0 H'FFA8 (Write) WDT_0 TCSR_0 H'FFA8 (Read) WDT_0 TCNT_0 H'FFA8 (Write)
Page 978 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States IIC_0 SARX_0 H'FFDE IIC_0 ICMR_0 H'FFDF IIC_0 SAR_0 H'FFDF IIC_1 ICDR_1 H'FECE (RELOCATE = 1) IIC_1 SARX_1 H'FECE (RELOCATE = 1) IIC_1 ICMR_1 H'FECF (RELOCATE = 1) IIC_1...
Page 979 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States IIC_2 ICMR_2 H'FE8F IIC_2 SAR_2 H'FE8F IIC_0 ICRES_0 H'FEE6 PS2_0 KBCR1_0 H'FEC0 PS2_0 KBTR_0 H'FEC1 PS2_0 KBCRH_0 H'FED8 PS2_0 KBCRL_0 H'FED9 PS2_0 KBBR_0 H'FEDA PS2_0 KBCR2_0...
Page 980 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States SCIFADRH H'FDC4 SCIFADRL H'FDC5 LADR4H H'FDD4 LADR4L H'FDD5 IDR4 H'FDD6 ODR4 H'FDD7 STR4 H'FDD8 HICR4 H'FDD9 SIRQCR2 H'FDDA SIRQCR3 H'FDDB TWR0MW H'FE20 TWR0SW H'FE20 TWR1 H'FE21...
Page 981 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States LADR3H H'FE34 LADR3L H'FE35 SIRQCR0 H'FE36 SIRQCR1 H'FE37 IDR1 H'FE38 ODR1 H'FE39 STR1 H'FE3A SIRQCR4 H'FE3B IDR2 H'FE3C ODR2 H'FE3D STR2 H'FE3E HISEL H'FE3F HICR0 H'FE40...
Page 982 Section 27 List of Registers Register Number of Data Bus Access Module Abbreviation Bits Address Width States SCIF FFCR H'FC22 SCIF FLCR H'FC23 SCIF FMCR H'FC24 SCIF FLSR H'FC25 SCIF FMSR H'FC26 SCIF FSCR H'FC27 SCIF SCIFCR H'FC28 FCCS H'FEA8 FPCS H'FEA9 FECS...
Page 983: Section 28 Electrical Characteristics
Section 28 Electrical Characteristics Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 lists the absolute maximum ratings. Table 28.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* –0.3 to +4.3 Input voltage (except ports 7, D, A, G, I, PE4, –0.3 to V + 0.3 PE2 to PE0, P97, P86, P52, and P42)
Page 984: Dc Characteristics
Section 28 Electrical Characteristics 28.2 DC Characteristics Table 28.2 lists the DC characteristics. Table 28.3 lists the permissible output currents. Table 28.4 lists the bus drive characteristics. Table 28.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV...
Page 985 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV = 0 V Item Symbol Min. Typ. Max. Unit Test Conditions ...
Page 986 Section 28 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connecting to the power supply (V ).
Page 987 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (4) Using FSI Function Conditions: V = 3.0 V to 3.6 V, V = 0 V Item Symbol Min. Typ. Max. Unit Test Conditions × 0.7   Input high voltage PB7 to PB4 + 0.3 −...
Page 988 Section 28 Electrical Characteristics Table 28.4 Bus Drive Characteristics Conditions: V = 3.0 V to 3.6V, V = 0 V Applicable Pins: SCL0, SDA0, SCL1, SDA1, SCL2, SDA2, ExSCLA, ExSDAA, ExSCLB, and ExSDAB (bus drive function selected) Item Symbol Min. Typ.
Page 989: Ac Characteristics
Section 28 Electrical Characteristics This LSI 600 Ω Ports 1 to 3, C and D Figure 28.2 LED Drive Circuit (Example) 28.3 AC Characteristics Figure 28.3 shows the test conditions for the AC characteristics. C = 30pF : All ports = 2.4 kΩ...
Page 990: Clock Timing
Section 28 Electrical Characteristics 28.3.1 Clock Timing Table 28.5 shows the clock timing. The clock timing specified here covers clock output (φ) and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 25, Clock Pulse Generator.
Page 991 Section 28 Electrical Characteristics EXTAL DEXT OSC1 φ Figure 28.5 Oscillation Stabilization Timing φ IRQi ( i = 0 to 15 ) KINi ( i = 0 to 15 ) WUEi ( i = 8 to 15 ) OSC2 PS2AC to PS2DC Figure 28.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev.
Page 992: Control Signal Timing
Section 28 Electrical Characteristics 28.3.2 Control Signal Timing Table 28.6 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD can be operated based on the subclock (φ = 32.768 kHz).
Page 993 Section 28 Electrical Characteristics φ NMIS NMIH NMIW IRQi (i = 0 to 15) IRQW IRQS IRQH Edge input IRQS Level input IRQS IRQH KINi (i = 0 to 15) WUEi IRQW (i = 0 to 15) Figure 28.8 Interrupt Input Timing Rev.
Page 994: Timing Of On-Chip Peripheral Modules
Section 28 Electrical Characteristics 28.3.3 Timing of On-Chip Peripheral Modules Table 28.7 shows the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer (WDT_1) only.
Page 995 Section 28 Electrical Characteristics Test Item Symbol Min. Max. Unit Conditions  Input clock rise time Figure 28.20 SCKr  Input clock fall time SCKf  Transmit data delay time (synchronous) Figure 28.21  Receive data setup time (synchronous)  Receive data hold time (synchronous) ...
Page 996 Section 28 Electrical Characteristics φ TOCD Output compare outputs* TICS Input capture inputs* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, and TIOCD0 Figure 28.10 TPU Input/Output Timing φ TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 28.11 TPU Clock Input Timing φ...
Page 997 Section 28 Electrical Characteristics φ TMRS TMI_0, TMI_1 TMI_X, TMI_Y Figure 28.14 8-Bit Timer Reset Input Timing φ TCMS TCMCYI TCMMCI Figure 28.15 TCM Input Setup Time φ TCMCKS TCMCKI TCMCKW TCMCKW Figure 28.16 TCM Clock Input Timing φ TDPS TDPCYI TDPMCI Figure 28.17 TDP Input Setup Time...
Page 998 Section 28 Electrical Characteristics φ TDPCKS TDPCKI TDPCKW TDPCKW Figure 28.18 TDP Clock Input Timing φ PWOD PWMU5A to PWMU0A, PWMU5B to PWMU0B, PWX1, PWX0 Figure 28.19 PWMU, PWMX Output Timing SCKW SCKr SCKf SCK1 Scyc Figure 28.20 SCK Clock Input Timing SCK1 TxD1 (transmit data)
Page 999 Section 28 Electrical Characteristics FSICK FSICK FSISS FSIDO FSIDI Figure 28.22 FSI Input/Output Timing Table 28.8 PS2 Timing = 0 V, φ = 8 MHz to maximum operating frequency Conditions: = 3.0 V to 3.6 V, V Standard Value Test Conditions Remarks Item Symbol Min.
Page 1000 Section 28 Electrical Characteristics (1) R eceive φ KBIS KBIH KCLK/KD* (2) Transmit (a) φ KBOD KCLK/KD* Transmit (b) KCLK/KD* Note: * KCLK : PS2AC to PS2DC KD : PS2AD to PS2DD Figure 28.23 PS2 Timing Rev. 1.00 Apr. 28, 2008 Page 974 of 994 REJ09B0452-0100...

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